JPH11338567A - Reference voltage generation circuit - Google Patents

Abstract

(57) [Problem] To provide a reference voltage generating circuit that stabilizes to a desired voltage at a low current without a control signal during a start-up period. A differential circuit having a current mirror transistor and outputting a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal, and outputting a reference voltage from a voltage source A reference voltage output terminal for connecting, a reference voltage output terminal, a plurality of resistance elements, a circuit for determining the reference voltage output, and a current to the resistance element by the output voltage of the differential circuit A first N-channel transistor for controlling, and a second N-channel transistor for supplying a current to the resistance element during a start-up period for generating a reference voltage;
The supply of the gate voltage of the channel transistor is connected to the gate of the current mirror transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit incorporated in a liquid crystal driver circuit for driving a liquid crystal panel used in a portable terminal and used for generating a power supply for a liquid crystal.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional reference voltage generating circuit is formed by connecting a plurality of differential circuits 1, PN junctions 2, and PN junctions having the same characteristics as PN junctions 2 in parallel. A first N-channel transistor 5, a first P-channel transistor 7, and a second P-channel transistor 5 for controlling current to the resistance element by the junction group 3, the resistance elements Rba4, Rbb9, Rbc10, and the output voltage of the differential circuit 1. It comprises a channel transistor 8 and a third P-channel transistor 6 used at the start of operation.

The output of the differential circuit 1 is connected to the gate of a first N-channel transistor 5 and a third P-channel transistor 6
The drain of the first N-channel transistor 5 is connected to the drain and gate of the first P-channel transistor 7 and the gate of the second P-channel transistor 8, and the drain of the second P-channel transistor 8 Is connected to one terminal of each of two resistance elements Rbb9 and Rbc10, and another one terminal not connected to the drain of the second P-channel transistor 8 of the resistance element is connected to the PN junction 2 and the resistance element Rba4, respectively. The other end of the PN junction 2 is connected to the VSS power supply, the resistance element Rba4 is connected to the PN junction group 3, and the PN junction group 3
Is connected to a VSS power supply.

Next, the operation of the reference voltage generation circuit will be described. In this reference voltage generation circuit, the voltage of the inverting input terminal is made equal to the voltage of the non-inverting input terminal by performing negative feedback to the differential circuit 1.

Since the forward voltage of the PN junction is smaller as the current is smaller, the voltage of the PN junction group 3 is lower than that of the PN junction group 3 when compared with the PN junction group 3. The voltage obtained by adding the voltage drop of the resistance element Rba4 to the forward voltage of the PN junction group 3 is compared with the PN junction 2, and the voltages are matched.

The forward voltage V of the PN junction due to a change in current
pn changes by ln as in (Equation 1), Vpn = kT / q × ln (Ipn / Is) (Equation 1) The voltage Vrba of the resistance element is as follows (Equation 2): Vrba = Irba × Rrba · (Equation 2) Since the change is linear, the change in the voltage drop of the resistance element Rba4 is larger, so that control can be performed by adjusting the current flowing through the resistance element Rba4.

Here, k is the Boltzmann constant, T is the absolute temperature, q is the charge of electrons, Ipn is the current flowing through the PN junction, Is is the saturation current of the PN junction, and Irba is the resistance element R.
In the current flowing through ba4, Rrba is the resistance value of the resistance element Rba4. To explain this with a mathematical expression, the forward voltage of the PN junction 2 is Vpn2, and the forward voltage of the PN junction group 3 is Vpn.
Assuming that the voltage drop of pn3 and the resistance element Rba4 is Vrba, Vpn2 = Vpn3 + Vrba (Equation 3). The current flowing through the PN junction 2 is I2, and the PN junction group 3
Is I3, and the number of PN junctions in the PN junction group 3 is N, (Equation 1), (Equation 2), and (Equation 3).
From kT / q × ln (I2 / Is) = kT / q × ln (I3 / N / Is) + I3 × Rrba kT / q × ln (I2 × N / I3) = I3 × Rrba (Equation 4) become.

Now, assuming that the resistance values of Rbb9 and Rbc10 are equal, if the voltages of the inverting input terminal and the non-inverting input terminal of the differential circuit 1 match, Rbb9 and Rbc1
0 are equal, I2 = I3 = Ir
become. Thus, from (Equation 4), kT / q × ln (N) = I3 × Rrba I3 = kT / q × In (N) / Rrba (Equation 5), and the current flowing through the resistance element Rba4 is adjusted. It can be seen that control can be performed by this.

However, the stability conditions for matching the voltages of the inverting input terminal and the non-inverting input terminal of the differential circuit 1 are as follows: the current is obtained from (Equation 5) and the current flows through the circuit formed by the PN junction and the resistance element. Since there are two points when no power is supplied, the circuit may stabilize in a state where no current flows unless a circuit current flows when the power is turned on. Since the reference voltage generation circuit needs to avoid this state, the following measures are taken.

FIG. 4 is a timing chart showing an operation sequence of the reference voltage generation circuit. In a start period starting from t = 0, the third P-channel transistor 6 is turned on by a START signal, and the gate voltage of the first N-channel transistor 5 is increased to flow a drain current. When the current of the first N-channel transistor 5 flows, the first P channel
A current flows through the channel transistor 7 and the second P-channel transistor 8, and a current flows through a circuit formed by the PN junction and the resistance element. When the operation returns to the normal operation after the start-up period, the current is stabilized from the current flowing state, so that the condition is satisfied under the condition of (Equation 5).

[0011]

In the conventional reference voltage generating circuit as described above, the third N-channel transistor 6 is forcibly turned on by a dedicated control signal during the start-up period, thereby forcibly setting the first N-channel transistor. The drain current of the channel transistor 5 flows, and the first P-channel transistor 7 and the second
However, there is a problem that a large current flows through the P-channel transistor 8.

[0012] Therefore, the present invention, during the start-up period,
An object of the present invention is to provide a reference voltage generating circuit that stabilizes at a desired voltage with a low current without a control signal.

[0013]

In order to achieve the above object, the present invention has a current mirror transistor, and is adapted to respond to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal. A differential circuit that outputs a voltage, a reference voltage output terminal for outputting a reference voltage from a voltage source, and a circuit that is connected to the reference voltage output terminal and that has a plurality of resistance elements and determines a reference voltage output A first N-channel transistor for controlling a current to the resistance element by an output voltage of the differential circuit; and a second N-channel transistor for supplying a current to the resistance element during a startup period for generating a reference voltage. An N-channel transistor, wherein the second N
The supply of the gate voltage of the channel transistor is connected to the gate of the current mirror transistor.

According to the above structure, the drain of the second N-channel transistor is connected in parallel with the drain of the first N-channel transistor, and the gate of the current mirror transistor of the differential circuit 1 is connected to the gate of the second N-channel transistor. A stable output current can be obtained by inputting the gate voltage, and the current always flows through the circuit consisting of the PN junction and the resistance element.
It is possible to obtain a reference voltage generation circuit that stabilizes at a desired voltage with a low current without a control signal.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of a reference voltage generating circuit according to a first embodiment of the present invention. The reference voltage generation circuit is as shown in FIG.
A differential circuit 1, a PN junction 2, a PN junction group 3 formed by connecting a plurality of sets of PN junctions having the same characteristics as the PN junction 2 in parallel, resistance elements Rba4, Rbb9, Rbc10, and a differential circuit 1.
A first N-channel transistor 5, a first P-channel transistor 7, a second P-channel transistor 8, and a PN
It comprises a junction and a second N-channel transistor 11 for keeping the circuit current of the circuit made of the resistance element flowing.

The output of the differential circuit 1 is connected to the gate of the first N-channel transistor 5, the gate of the second N-channel transistor 11 is connected to the gate voltage of the current mirror transistor of the differential circuit 1, The drain of the N-channel transistor 5 is connected to the drain of the second N-channel transistor 11 and the first P-channel transistor 7.
Drain, gate and second P-channel transistor 8
Of the second P-channel transistor 8
Is connected to one terminal of each of the two resistance elements Rbb9 and Rbc10, and another one terminal not connected to the drain of the second P-channel transistor 8 of the resistance element is connected to the PN junction 2 and the resistance element Rba4, respectively. The other end of the PN junction 2 is connected to the VSS power supply, and the resistance element Rba4 is connected to the PN junction group 3,
The other end of the junction group 3 is connected to a VSS power supply.

Next, the operation of the reference voltage generating circuit will be described. Since the basic operation is the same as that of the conventional example, the description is omitted. The second N-channel transistor 11 receives the gate voltage of the current mirror transistor of the differential circuit 1 and allows a stable drain current to flow. The drain current of the transistor during the saturation operation is Id = β / 2 × (Vgs−Vt) (Vgs−Vt) (6) β / 2 = 1/2 × μnCox × W / L (5) 7) Assuming that the drain current of the first P-channel transistor is Idp1 and the drain current of the second P-channel transistor is Idp2, Idp1 = βp1 / 2 × (Vgs−Vt) (Vgs−Vt) (Equation 8) Idp2 = βp2 / 2 × (Vgs−Vt) (Vgs−Vt) (Equation 9) where, for the current In2 of the second N-channel transistor,
The circuit current Ipn of the circuit formed by the PN junction and the resistance element is In2 = Idp1 (Equation 10) Ipn = Idp2 (Equation 11) From Equations 8 and 9, Idp2 = βp2 / βp1 × From Idp1 (Equation 12), Ipn = βp2 / βp1 × In2 (Equation 13). Thereby, the second N-channel transistor 1
When a current always flows through the circuit No. 1, a current multiplied by βp2 / βp1 flows as a minimum current through a circuit formed by a PN junction and a resistance element.

[Second Embodiment: Corresponding to Claim 2] FIG. 2 is a circuit diagram of a reference voltage generating circuit according to a second embodiment of the present invention. The reference voltage generation circuit is as shown in FIG.
N for reference voltage connecting differential circuit 1 with gate and drain
A reference voltage N formed by connecting in parallel a plurality of sets of a reference voltage N-channel transistor having the same characteristics as the channel transistor 12 and the reference voltage N-channel transistor 12.
Channel transistor group 13 and resistance elements Rba4, Rb
b9, Rbc10, a first N-channel transistor 5, a first P-channel transistor 7, a second P-channel transistor 8, and a reference voltage for controlling a current to the resistance element by an output voltage of the differential circuit 1. And a second N-channel transistor 11 for continuously flowing a circuit current of a circuit made of a resistance element.

The output of the differential circuit 1 is connected to the gate of the first N-channel transistor 5, the gate of the second N-channel transistor 11 is connected to the gate voltage of the current mirror transistor of the differential circuit 1, The drain of the N-channel transistor 5 is connected to the drain of the second N-channel transistor 11 and the first P-channel transistor 7.
Drain, gate and second P-channel transistor 8
Of the second P-channel transistor 8
Is connected to one terminal of each of two resistance elements Rbb9 and Rbc10, and another one terminal not connected to the drain of the second P-channel transistor 8 of the resistance element is connected to the N-channel transistor 12 for reference voltage.
And the resistor Rba4, the other end of the reference voltage N-channel transistor 12 is connected to the VSS power supply, and the resistor Rba4 is connected to the reference voltage N-channel transistor group 13, and the reference voltage N-channel transistor group The other end of 13 is connected to the VSS power supply.

Next, the operation of the reference voltage generating circuit will be described. The gate and drain of the reference voltage N-channel transistor are connected and perform a saturation operation. The drain current is expressed by (Equation 6), and the voltage is expressed by Vgs = Vt + √ (2Id / β) (Equation 14). As in the case of the PN symbol, the amount of change in the resistance element due to the current is smaller. Because it is large, control by adjusting the current is possible. The other operation is the same as that of the first embodiment, and thus the description is omitted.

[0022]

According to the reference voltage generation circuit of the present invention, it is possible to obtain a reference voltage generation circuit that stabilizes at a desired voltage with a low current without a control signal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a reference voltage generating circuit according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing a configuration of a reference voltage generating circuit according to a second embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of an example of a conventional reference voltage generation circuit.

FIG. 4 is a timing chart showing an operation of a control signal START when power is supplied to a conventional reference voltage generation circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 differential circuit 2 PN junction 3 PN junction group 4 resistive element Rba 5 first N-channel transistor 6 third P-channel transistor 7 first P-channel transistor 8 second P-channel transistor 9 resistive element Rbb 10 resistive element Rbc 11 Second N-channel transistor 12 N-channel transistor for reference voltage 13 N-channel transistor group for reference voltage

Claims (3)

[Claims] 1. A differential circuit having a current mirror transistor and outputting a voltage corresponding to a difference between a voltage applied to a non-inverting input terminal and a voltage applied to an inverting input terminal, and outputting a reference voltage from a voltage source A reference voltage output terminal for connection, and a plurality of resistance elements connected to the reference voltage output terminal,
A circuit for determining a reference voltage output; a first N-channel transistor for controlling a current to the resistance element by an output voltage of the differential circuit; and a resistance element to the resistance element during a startup period for generating a reference voltage. And a second N-channel transistor for supplying a current, wherein the supply of the gate voltage of the second N-channel transistor is connected to the gate of a current mirror transistor. 2. The circuit for determining a reference voltage output is P
2. The reference voltage generating circuit according to claim 1, further comprising an N junction. 3. A circuit for determining a reference voltage output, comprising:
2. The reference voltage generating circuit according to claim 1, further comprising an N-channel transistor having a gate and a drain connected to each other.