JPH11355236A - Stuff synchronous multiplex communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide stuff synchronous multiplex communication equipment which reduces a slip frequency and improves transmission efficiency and transmission quality. SOLUTION: A first station and a second station connected through a transmission line are made to have a transmission part and a reception part respectively. The reception part has memory circuits 105 and 205. A writing address and a reading address of these memory circuits 105 and 205 are monitored by a comparison decision circuit and oscillation circuits 103 and 203 for variable controlling a transmission frequency of the transmission part are equipped with.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication device having a clock which is a reference in each country and performing international digital communication, and more particularly to a stuff synchronous communication device of a satellite communication system and its multistage relay system.

[0002]

2. Description of the Related Art In digital satellite communications and international communications, staff-synchronized multiplex communications are employed. The stuff synchronization means that when multiplexing digital signals generated from each device, the signals are temporarily stored in a memory and read out with a common clock signal that is slightly faster than the signal to be multiplexed, thereby converting the signals into the same speed. Refers to the method. The difference is compensated by inserting a useless pulse (stuff pulse) as necessary (refer to the “Latest Information Communication Glossary” issued by the Telecommunications Association).

FIG. 4 is a simple block diagram of a conventional stuff synchronous multiplex communication device. This shows a state where the first station and the second station are connected by the stuff synchronous multiplex communication device. The first station includes a multiplexing circuit 101 and multiplexes the input main signal a1 and additional information including stuff information bits (or stuff pulses). It has a phase monitoring circuit 102 to which a signal a2 of an oscillation circuit 403 that oscillates a frequency (radio frequency: ft1) higher than the main signal a1 by additional information is input. The phase monitoring circuit 102 monitors the phase difference between the two signals a1 and a2 and inputs the signal a3 to the multiplexing circuit 101. The output signal a4 of the multiplexing circuit 101 is sent to the second station via the propagation path.

The second station establishes frame synchronization with the signal a5 to which jitter has been added by the propagation path, and reproduces the main signal (memory write signal) a6.
And a memory circuit 205 for storing the main signal a6. This memory circuit 205 removes jitter by reading with the output signal a8 of the oscillation circuit 206 at the frequency fr2, monitors the write phase (address) of a6 and the read phase (address) of a9, and performs write and read operations. When the address relation becomes a predetermined relation, the transmission frequency control information of a7 is transmitted.

On the other hand, the transmitting section of the second station and the receiving section of the first station have the same configuration as the transmitting section of the first station and the receiving section of the second station, respectively. That is, the transmission unit of the second station includes the multiplexing circuit 201, the phase monitoring circuit 202, and the oscillation circuit 503. Further, the receiving unit of the first station includes a separation circuit 104, a memory circuit 105, and an oscillation circuit 106.

In digital radio transmission, information transmission is performed by multiplexing various types of additional information into a main signal. For example, there are a frame synchronization signal for establishing frame synchronization between a transmitting station and a receiving station, a digital service signal, a control signal, an alarm signal, and a coded redundant signal for correcting a propagation path error. In order to add these additional information, the main signal (a
1) Frequency higher than additional information by the amount of additional information (radio frequency: ft
1) It has an oscillation circuit that oscillates.

When the radio frequency and the frequency of the main signal have an asynchronous relationship, or when a plurality of main signals are connected from an asynchronous network, it is necessary to adopt a stuff synchronization method.
In the stuff synchronization method, stuff bits are allocated on a radio frame by a predetermined number of bits. The phase is adjusted by assigning a stuff bit to the main signal (raw data) or making it a useless bit according to the phase monitoring result of monitoring the phase of the main signal and the radio frequency to advance or delay the phase. This is a method of synchronizing an asynchronous signal and transmitting the signal.

[0008] On the other hand, satellite communication for international communication has a clock which is a reference in each country. The transmitted signal contains jitter due to the propagation path and Doppler effect,
Since the quality is degraded, it is necessary to transfer the signal with a stabilized reference clock that each country has. At this time,
Since the transmission clock and the reception clock are asynchronous, a slip (data loss) generally occurs when the clocks are switched.

The clock transfer is realized by writing in the memory circuit with the transmitted clock and reading out with the reference clock on the receiving side. This memory circuit is called a Doppler Pregio crossover buffer and has a memory capacity M
(Bit) and the frequency difference (fw-fr) (Hz) determine the slip frequency. Due to this slip, the signal is momentarily interrupted, and sound and images are disturbed.

[0010]

In the prior art, the oscillation frequencies ft1, ft2 of the oscillation circuits 403, 503 in FIG.
Is fixed, slip occurs as described above. In international communications, each country has a stabilized reference clock, and each country operates with the stabilized clock (pre-gio crossover operation), so it synchronizes with the frequency of the digital signal from the transmitting country. However, since the data is reproduced with the stabilized reference clock independently provided in the receiving country, slip (data loss) occurs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a stuff synchronous multiplex communication which improves the transmission effect and transmission quality of international communication by reducing the slip frequency determined by the memory capacity of the buffer and the frequency difference between the transmitting and receiving stations. It is to provide a device.

[0012]

In order to solve the above-mentioned problems, a stuff synchronous multiplex communication apparatus according to the present invention has the following characteristic configuration.

(1) In a stuffed synchronous multiplex communication apparatus having a transmitting section and a receiving section respectively at a first station and a second station connected via a propagation path, a memory means for absorbing jitter at a receiving station, and the memory Means for monitoring the write and read addresses to the means and determining whether to advance or delay with respect to a preset address relationship; and using a radio time slot to transmit a control signal based on the result of the determination by the comparison and determination means. A stuff-synchronous multiplex communication apparatus comprising: a transmission unit that transmits a signal to the transmission unit; and a transmission frequency variable unit that controls a transmission frequency based on the control signal of the transmission unit.

(2) The stuff-synchronous multiplex communication apparatus according to (1), wherein the memory means of the receiving station uses a stabilized reference clock asynchronous with the clock of the transmitting station to perform a pre-Gross Cloner operation.

(3) The processing time for variably controlling the transmission frequency is shortened, so that the memory capacity of the memory means for performing the pre-geosc operation is reduced and the transmission delay time is shortened. Multiplex communication device.

(4) The stuff synchronous multiplex communication apparatus of (1), (2) or (3), wherein a satellite and a terrestrial radio communication line are connected in multiple stages as the propagation path.

(5) The variable control of the transmission frequency is performed based on the absolute value of the difference between the write and read addresses of the memory means latched at the timing of the frame pulse (1), (2), (3) Or the stuff synchronous multiplex communication device of (4).

[0018]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a stuff synchronous multiplex communication apparatus according to a preferred embodiment of the present invention.

First, a description will be given, with reference to FIG. 1 showing a block diagram of one embodiment of a stuff synchronous multiplex communication apparatus according to the present invention. Since this stuff synchronous multiplex communication apparatus uses the same elements as the conventional apparatus of FIG. 4, the corresponding elements are denoted by the same reference numerals.

The transmitting section of the first station includes a multiplexing circuit 101 and a phase monitoring circuit 102. The receiving unit is also a separation circuit 1.
04, a memory circuit 105, and an oscillation circuit 106. On the other hand, the receiving unit of the second station includes the separation circuit 204 and the memory circuit 2
05 and the oscillation circuit 206, and the transmission unit includes the multiplexing circuit 2
01, which is the same as the conventional device of FIG. 4 in that it includes the phase monitoring circuit 202.

However, as is apparent from comparison between the block diagrams of FIGS. 1 and 4, the stuff synchronous multiplex communication apparatus of the present invention shown in FIG. 1 has the following differences. The separation circuit 104 of the reception unit of the first station separates a16 in the additional information, and controls the oscillation frequency of the oscillation circuit 103 of the transmission unit based on this a16. Further, the oscillation circuit 203 of the transmission unit of the second station has a12
Is input to the phase monitoring circuit 202.

Next, in the stuff synchronous multiplex communication apparatus having the configuration shown in FIG. 1, opposing first and second stations are connected to the stuff synchronous multiplex communication apparatus, and a signal transmitted by the first station is transmitted to the second station. The procedure for reading with the stabilized reference clock will be described.

The transmitting section of the first station receives the input main signal a1
A multiplexing circuit 101 for multiplexing additional information including a stuff information bit, an oscillation circuit 103 for changing an oscillation frequency ft1 by a control signal from an opposite station (second station),
a phase monitoring circuit 102 for monitoring the phase difference between a1 and a2.

On the other hand, the receiving section of the second station includes a fixed oscillation circuit 206 for oscillating a stable reference clock (ft2) a8,
Frame synchronization is established for a5 to which jitter has been added by the propagation path, and it is possible to recognize whether the stuff bit is a useless bit of the main signal by the stuff information bit "1" or "0" in the separated additional information. The main signal (separation circuit 204 for reproducing memory write signal a6, jitter is removed by reading with a8, write phase (address) of a6,
The memory circuit 205 monitors the read phase (address) of a9 and sends out the transmission frequency control information of a7 when the relationship between the write and read addresses becomes a predetermined relationship.

On the other hand, the transmitting section of the second station has the same configuration as the transmitting section of the first station. That is, the multiplexing circuit 201
1, which also multiplexes a control signal a7 for changing the transmission frequency of the first station as additional information. Phase monitoring circuit 2
02 and the oscillation circuit 203 have the same functions as 102 and 103, respectively, and the signals a14 and a15 are equivalent to a4 and a5, respectively.

The receiving sections of the first station are the same as the receiving sections of the second station, respectively. The separating circuit 104 separates a16 in the additional information and inputs the separated a16 to the oscillating circuit 103 of the transmitting section.
3 is controlled. The output of the separation circuit 104 is stored in the memory circuit 105.

Next, the operation or function of the stuffed synchronous multiplex communication apparatus of FIG. 1 will be described in detail. First, the slip period will be described. When the memory capacity of the memory circuit 205 is M,
The write frequency is fw, and the read frequency (reference clock frequency) is fr. The slip period Tslip is represented by the following equation. Tslip = (fr × M / 2) ÷ | fw−fr | In the case where fw and fr are constant as in the related art, it can be seen from the above equation that if M is increased, Tslip is lengthened. However, in this case, a slip always occurs in the Tslip cycle.

Here, even in a system in which M is the same as the conventional system,
By making fw higher, lower, or fluctuate within the stuff rate fluctuation, Tslip can be improved as compared with the conventional case. In a stuff synchronizer that cycles with the transmission signal,
When the stuff ratio is changed, it is necessary to consider stuff jitter at the time of signal reproduction at the receiving end. However, especially in the case of the Pre-Gross Cloner operation, this consideration is unnecessary because the receiving end is configured to read out with a unique stabilized reference clock.

Next, the transmission frequency control signal (a7 to a16)
Will be described. There are three modes of this control: raising the frequency, lowering the frequency, and maintaining the frequency. At least the and forms are necessary. As a specific example of the operation, one control signal is allocated to each one bit, and the same control signal is transmitted in five time slots in a basic unit of a frame in consideration of an error in a radio channel, and a majority decision is made at a receiving end. Is used to determine the control value. Here, the time slots for use are e1 to e5, and the time slots for use are d1 to d5. At the receiving end, e and d each make a 3/5 majority decision. This is due to the propagation path error e
This means that erroneous control is not caused even if two of 1 to e5 are wrong. When the determination result of e and d is “1, 0”, control to increase the frequency is performed. When the determination result is “0, 1”,
Execute the control to lower the frequency. When the frequency is "1, 1" or "0, 0", the frequency is maintained.

Next, the operation of transmitting the transmission frequency control information a7 will be described. In FIG. 1, the control signal a7 is transmitted as follows.
A6 write phase (address) to memory circuit 205
And the read phase (address) of a9 is monitored, and a control signal a7 is sent out when the address relation between write and read becomes a relation determined to suppress the slip.

This operation will be described in detail below with reference to FIGS. FIG. 2 shows the memory circuit 205 of FIG.
It is a detailed block diagram of. It has a memory 301 to which multiplexed data (memory write data) a6 of the received and reproduced wireless frame is input. It has a gate 303 for generating a memory write clock b3 generated from the clock a6 'of the multiplexed data a6, and writes the data to the memory 301 of the memory capacity M with the memory write clock b3. Further, the memory 301 reads and outputs the raw data a9 at the reference clock a8. The memory 301 stores a write address Aw
And the read address Ar are generated, and the comparison judgment circuit (COM
In P) 304, both addresses Aw and Ar are compared.

FIG. 3 is a timing chart for explaining the operation of each part of the memory circuit 205 shown in FIG. FIG. 3 shows an example of a radio frame in which additional information is 1 bit for 2 bits of raw data. The clock a6 'is input to the timing generation circuit 302 and the gate 303. The timing circuit (TIMGEN) 302 includes a gate signal b1 indicating a multiplexing time slot of additional information (information indicated by a hatched portion in a6) in the multiplexed data a6, and a frame pulse b2 indicating a multiplexing cycle of the radio frame. Is output. The gate 303 eliminates the clock a6 'by the gate signal b1 and generates a write clock b3 for writing raw data into the memory 301.

On the other hand, the memory 301 stores the write clock b
It has counters (not shown) for counting 3 and a8, respectively, and generates a write address Aw and a read address Ar. These addresses Aw and Ar and the frame pulse b2 are input to the comparison and determination circuit 304. This comparison determination circuit 304
The addresses Aw and Ar are latched at the timing of the frame pulse b2, and | Aw'-
Ar '| = N is calculated. An example in which this calculation result is N = M / 2 (Case 1) and an example in which N = M / 2 + 1 = Nmax (Case
The operation is performed as follows according to 2) and an example (Case 3) where N = M / 2-1 = Nmin. In Case 1, a control value for maintaining the transmission frequency is output. In Case 2, a control value for lowering the transmission frequency is output. In case 3, a control value for increasing the transmission frequency is output. This output signal is the frequency control signal a7.

The frequency control signal a7 must be multiplexed at an integral multiple of the radio frame multiplexing cycle. This is because, as described above, the receiving side has a majority decision circuit for suppressing propagation path errors.

Finally, the control amount (fstep) of the transmission frequency (fradio) will be described. The memory capacity is M, the write frequency is fw, the read frequency (reference clock frequency) is fr, the slip period is Tslip, and the effective time from when a frequency change is instructed by the frequency control signal a7 until a signal can be received at the controlled frequency. Is Twait. In this case, 1
The frequency control amount fstep in each control may have the following relationship. Tslip {(fr × M / 2)} | fw-fr | (1) fstep> | fw-fr | × K (2) K ≒ Tslip / Twait (integer) In the above expression, | fw-fr | Although the difference between the writing frequency and the reading frequency for the memory 301 is the frequency, fradio must be controlled within a fluctuation range in which stuff synchronization can be established in the first place.

Further, the radio frequency is radio, the reference frequency (raw data frequency) of the transmitting unit is f, the number of raw data in the radio frame multiplexing cycle is Nraw, the number of additional information raw data excluding stuff bits is Nadd, Assuming that the bit is 1 bit, f × (Nraw + Nadd + 1) / (Nraw + 1) ≦ fradio ≦ fx × (Nraw + Nadd + 1) / Nraw f = fw radio = fw + fstep fw × (m / n−1) ≦ fstep ≦ fw × (m / ( t-1) -1 (3) Nraw + Nadd + 1 = m, Nraw + 1 = n This is set in consideration of the above equations (1) to (3).

[0037]

As will be understood from the above description, the following effects can be obtained by the stuff synchronous multiplex communication device of the present invention. Since it has a variable control function of the transmission frequency and particularly variably controls the transmission frequency of the game using the time slot of the additional information, it is possible to suppress the periodic slip in the operation of the pre-Gross crossover. In addition, since the memory is read out with the stabilized reference clock, no jitter is output to the succeeding clock, so that the destuffing jitter generated in the stuff synchronous communication can be suppressed. Furthermore, since the memory is read out even with the stabilized reference clock and the jitter is not output to the succeeding stage, the jitter transmission characteristic of the transmission signal can be improved for each transmission section, and the deterioration of the output jitter characteristic can be prevented even in the case of multi-stage connection. Has a significant effect in practical use.

[Brief description of the drawings]

FIG. 1 is a block diagram of a preferred embodiment of a stuffed synchronous multiplex communication device of the present invention.

FIG. 2 is a detailed block diagram of a memory circuit of the stuffed synchronous multiplex communication device of FIG. 1;

FIG. 3 is a timing chart for explaining an operation of the memory circuit of FIG. 2;

FIG. 4 is a block diagram of a conventional stuff synchronous multiplex communication device.

[Explanation of symbols]

 101, 201 Multiplexing circuit 102, 202 Phase monitoring circuit 103, 203 Oscillating circuit 104, 204 Separating circuit 105, 205 Memory circuit 106, 206 Oscillating circuit 301 Memory 302 Timing generating circuit 303 Gate 304 Comparison / determination circuit

Claims (5)

[Claims] A first station and a second station connected via a propagation path.
In a stuff-synchronous multiplex communication apparatus having a transmitting unit and a receiving unit in a station, a memory means for absorbing jitter at a receiving station, and a write and read address to and from the memory means are monitored, and a predetermined address relationship is advanced. Or a comparing and judging means for judging a delay; a transmitting means for transmitting a control signal based on the judgment result of the comparing and judging means to a game station using a radio time slot; and controlling a transmission frequency based on the control signal of the transmitting means. A stuff synchronous multiplex communication device, comprising: 2. The stuff-synchronous multiplex communication according to claim 1, wherein said memory means of said receiving station uses a stabilized reference clock which is asynchronous with a clock of said transmitting station to perform a pre-Gross Cloner operation. apparatus. 3. The method according to claim 1, wherein the processing time for variably controlling the transmission frequency is shortened, so that the memory capacity of said memory means for performing the pre-geosc operation is reduced and the transmission delay time is shortened. 3. The stuff synchronous multiplex communication device according to 2. 4. The stuff synchronous multiplex communication apparatus according to claim 1, wherein a satellite and a terrestrial radio communication line are connected in multiple stages as the propagation path. 5. The variable transmission frequency control according to claim 1, wherein the write and read addresses of said memory means are based on an absolute value of a difference between values latched at a frame pulse timing. Or the stuff synchronous multiplex communication device according to 4.