JPH1139136A - Projection display device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a means for displaying an input video signal of a display pixel exceeding this pixel on a dot matrix display device having a small number of display pixels without dropping dots. SOLUTION: An input video signal S1 is sampled by a sampling and holding circuit 1 to obtain an output video signal S11,
Input to the LCD for projection display. The input is a horizontal start signal S by the display clock signal S12 in the horizontal direction.
13 to a horizontal end signal S16, and in the vertical direction, a vertical start signal S1 by a scanning signal S14.
Starting from 5, the display is performed up to the vertical end signal S17. By changing the relative periods of the input video signal of the horizontal start signal S13 and the vertical start signal S15 from the horizontal synchronization signal S2 and the vertical synchronization signal S3, the input video signal S1 is changed.
In the entire display screen, the position of the signal displayed on the actual display screen can be changed by scrolling, and the signal at an arbitrary position in the input signal screen can be displayed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a projection type display for scrolling and displaying an input video signal having a larger number of pixels than that determined by a dot matrix output from a personal computer or the like on a display device having a fixed dot matrix. Related to the device.

[0002]

2. Description of the Related Art A video signal output from a personal computer or the like is converted to an LC signal.
There are many uses such as performing a presentation on a large screen with a projection display device using D (liquid crystal display) or the like. However, in a dot matrix type display device such as a liquid crystal, the number of display pixels is determined by the dot matrix, and in order to display a video signal of a larger number of display pixels, it is necessary to perform pixel interpolation or the like by image processing using a frame memory. It is necessary to perform a number conversion, and even if such image processing is performed, there occurs a problem that a displayed line width differs depending on a place. Increasing the number of display pixels of a display device is not only technically difficult but also expensive and has economical problems.

[0003]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and provides a means for displaying an input video signal of a display pixel exceeding this pixel on a dot matrix display device having a small number of display pixels without dropping dots. The purpose is to provide.

[0004]

A sampling clock generation circuit corresponding to an input video signal, means for setting a horizontal and vertical display start position, and display of the dot matrix from the horizontal display start position A counting circuit for counting the number of sampling clocks corresponding to the number of pixels; a counting circuit for counting the number of scanning lines of the video signal corresponding to the number of display pixels from the display start position in the vertical direction of the dot matrix; A sampling circuit for sampling the video signal with a sampling clock corresponding to the dot matrix, and setting display start positions in the horizontal direction and the vertical direction, thereby increasing the number of display pixels larger than the number of display pixels determined from the dot matrix. An arbitrary position of an input video signal having a number can be displayed.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a projection display apparatus for displaying an image on a display device comprising a dot matrix, a circuit for generating a sampling clock corresponding to an input video signal, and means for setting display start positions in the horizontal and vertical directions are provided. A counting circuit for the number of sampling clocks corresponding to the number of display pixels from the display start position in the horizontal direction of the dot matrix, and the image corresponding to the number of display pixels from the display start position in the vertical direction of the dot matrix. A circuit for counting the number of scanning lines of a signal, and a sampling circuit for sampling the video signal with a sampling clock corresponding to the dot matrix counted by the counting circuit are provided, and the display start positions in the horizontal and vertical directions are set. Display pixels larger than the number of display pixels determined from the dot matrix. To be able to view an arbitrary position of the input video signal having a.

The setting range of the display start position by the setting means is a difference between the number of horizontal pixels of the video signal and the number of horizontal pixels of the dot matrix in the horizontal direction, and the number of vertical pixels of the video signal in the vertical direction. And the number of pixels in the vertical direction of the dot matrix.

A marker indicating a direction in which the display position of the video signal can move is displayed at a position where the display screen can move.

The sampling clock generating circuit has a PLL (phase locked loop) whose frequency division ratio can be set from outside.
A circuit for setting the frequency of the sampling clock in accordance with the number of display pixels of the input video signal.

The display device is an LCD (liquid crystal display) having a memory function such as a TFT (thin film transistor) type.

[0010] A line memory is provided for storing the sampled video signal for one scanning period and reading it out at the original sampling rate of the display device.

The number of display pixels determined from the dot matrix is 800.times.600 pixels, and the input video signal is 10 pixels.
24 × 768 pixels.

A means for counting a horizontal synchronization signal in a vertical synchronization period of an input video signal is provided, and the display is performed by detecting the number of display pixels of the video signal identified from the number of scanning lines of the video signal.

A remote controller is provided, and the display start position is set according to an input signal from the remote controller.

[0014] A means for compressing the number of display pixels of the input video signal is provided so that the entire video signal is displayed on the display device.

[0015] The compression by the compression means is obtained by sampling the input video signal with an original sampling clock of the display device.

[0016]

FIG. 1 is a circuit block diagram of a main part of an embodiment of a projection type video apparatus according to the present invention. FIG. 2A shows a display screen of an embodiment of the projection display apparatus according to the present invention.
It is a conceptual diagram when the display start position is an intermediate value that can be set, and (B) when the display start position is the maximum value that can be set. An input video signal S1 from a personal computer or the like is sampled by a sampling and holding circuit 1 to produce an output video signal S11, which is input to, for example, an LCD, which is a display device of a projection display device, and projected and displayed as a display screen 22. The input to the LCD starts in the horizontal direction from a horizontal start signal S13 by a display clock signal S12, and then ends in a horizontal end signal S1.
6 and display from the position of PS13 to PS16 on the display screen. In the vertical direction, the scanning signal S14 starts from a vertical start signal S15 and a vertical end signal S1.
7 and display from the position of PS15 to PS17 on the display screen. Horizontal start signal S13 and vertical start signal S1
5 is set by changing the relative period of the input video signal from the horizontal synchronization signal S2 and the vertical synchronization signal S3, so that the input signal screen 21 is a display screen when the entire input video signal S1 is displayed as it is. The position of a signal displayed on the actual display screen 22 can be changed by scrolling, and a signal at an arbitrary position in the input signal screen 21 can be displayed.

The sampling clock of the sampling and holding circuit 1 is generated by the PLL circuit 2 in synchronization with the horizontal synchronizing signal S2. The frequency division ratio of the fractionator of the PLL circuit is variable and set externally in accordance with the input signal. MPU
12, the horizontal synchronizing signal S2 and the vertical synchronizing signal S3 of the input video signal are input, and the number of horizontal synchronizing signals during the vertical period is counted by the procedure of the input signal pixel number detection processing section 14a. The number of display pixels of the signal S1 is identified. A frequency divider of the PLL circuit 2 is calculated from the identified number of display pixels to set a frequency divider. The counter 6 that initializes the sampling clock output from the PLL 2 with the horizontal synchronization signal S2 counts the count value set by the MPU 12, and outputs the horizontal start signal S13. Also, the counter 7 initialized by the horizontal start signal S13 counts the sampling clock output from the PLL 2 by the number of pixels in the horizontal direction determined by the dot matrix of the LCD, and outputs the horizontal end signal S16. Similarly, the horizontal synchronization signal S
2 is initialized by a vertical synchronizing signal.
The count value is set at 12, and the count value is counted, and the vertical start signal S15 is output. Also, the vertical start signal S15
The horizontal synchronizing signal S2 is initialized by the counter 11
And outputs the vertical end signal S17 by counting the number of pixels in the vertical direction determined by the dot matrix.

A horizontal display period signal is created by an FF (flip-flop) circuit 5 which is set by a horizontal start signal S13 and reset by a horizontal end signal S16, and this signal is used as a sampling clock output from the PLL 2 using the gate circuit 4. The gate is applied to obtain a horizontal display clock signal S12. Similarly, a vertical display period signal is generated by the FF circuit 8 which is set by the vertical start signal S15 and reset by the vertical end signal S17, and the horizontal synchronizing signal S2 is gated by the gate circuit 9 using this signal, and the scanning signal is output. S14 is obtained. The gate circuit 3 gates the sampling clock output from the PLL 2 with the horizontal display period signal and the vertical display period signal, samples the input video signal S1 at the output, and outputs the output video signal corresponding to the number of display pixels of the LCD. S11
Create

The MPU 12 has a display position setting processor 14b.
According to the above procedure, the set value of the display start position is obtained from the remote controller 13 or the like, and set in the counters 6 and 10 described above.
The setting range of the display start position to be set is PS13m which is a difference between the number of horizontal pixels of the input video signal S1 and the number of horizontal pixels of the dot matrix of the LCD in the horizontal direction, and the number of vertical pixels of the input video signal in the vertical direction. The display screen 22 is limited to the range of the input signal screen 21 as PS15m, which is the difference between the number of pixels in the pixel matrix in the vertical direction and that of the dot matrix of the LCD. A marker 2 that is set from the MPU 12 to the on-screen display circuit 15 and indicates a direction in which the display screen 22 can move.
2a, 22b, 22c and 22d are displayed. This marker displays, for example, all the two-way arrows 22a, 22b, 22c, and 22d when the marker can be moved in either direction, and shows the one-way arrows 22a and 22c when the marker can be moved in only one direction.
And so on.

The LCD as the above display device has a T
By having an FT (thin film transistor) type memory function or the like, when displaying an input video signal having display pixels larger than the number of display pixels determined by the dot matrix, a so-called flicker caused by a so-called blanking period becomes longer. Can be displayed without the influence of the above.

The output video signal S11 is further stored for one scanning period, and a line memory (not shown) is read out at an original sampling rate of the LCD as a display device.
It becomes the original of the CD, and it is not necessary to take special consideration such as raising the operating frequency of the horizontal driver of the LCD.

The number of display pixels of the LCD determined from the dot matrix is 800 × 600 pixels, and the input video signal is 10 pixels.
With 24 × 768 pixels, it is possible to display a video signal of a personal computer or the like that is frequently used. PLL circuit 2 that generates a sampling clock as described above
Can be set from the MPU 12, so that the circuit can be used as it is for either input.

The remote controller 13 is provided with an input section for instructing the full-screen display mode. When the full-screen display mode is designated, regardless of the display pixels of the input video signal S1, the remote control 13 uses the original sampling clock of the LCD. Sampling and display. As described above, when the number of pixels of the input video signal is large, the number of display pixels is compressed and displayed. In this case, the display screen may be broken or the like. However, since the whole image of the input video signal can be grasped, it is possible to scroll to a desired portion in the above-described display mode and display in detail.

[0024]

As described above, the sampling clock generation circuit corresponding to the input video signal, the horizontal and vertical display start position setting means, and the horizontal and vertical display start positions of the dot matrix are used. A counting circuit for counting the number of sampling clocks corresponding to the number of display pixels; a counting circuit for counting the number of scanning lines of the video signal corresponding to the number of display pixels from the display start position in the vertical direction of the dot matrix; By providing a sampling circuit for sampling the video signal with a sampling clock corresponding to the dot matrix counted in the above, and setting the display start position in the horizontal direction and the vertical direction, the number of display pixels is larger than the number of display pixels determined by the dot matrix. To be able to display any position of the input video signal with display pixels Inexpensive display device using a simple circuit, it becomes possible to display not leak information number of display pixels with many input video signal.

[Brief description of the drawings]

FIG. 1 is a main part circuit block diagram of an embodiment of a projection type video apparatus according to the present invention.

FIG. 2A shows an embodiment of a projection type video apparatus according to the present invention.
(B) is a conceptual diagram in the case where the display start position is the maximum value that can be set.

[Explanation of symbols]

 S1 Input video signal S2 Horizontal synchronization signal S3 Vertical synchronization signal S11 Output video signal S12 Display clock signal S13 Horizontal start signal S14 Scan signal S15 Vertical start signal 1 Sampling hold circuit 2 PLL (phase locked loop) circuit 3, 4, 9 Gate circuit 5, 8 FF circuit 6, 10, 11 counter 12 MPU 13 remote controller 14a input signal pixel number detection processing unit 14b display start position setting processing unit 15 on-screen display circuit 21 input signal display screen 22 display screen

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code FI H04N 5/74 H04N 5/74 B

Claims (11)

[Claims] 1. A projection display device for displaying an image on a display device comprising a dot matrix, comprising: a generation circuit for a sampling clock corresponding to an input video signal; setting means for setting a display start position in a horizontal direction and a vertical direction; A circuit for counting the number of sampling clocks corresponding to the number of display pixels from the display start position in the horizontal direction of the dot matrix; and a circuit for counting the number of display pixels from the display start position in the vertical direction of the dot matrix. By providing a sampling circuit for counting the number of scanning lines and a sampling circuit for sampling the video signal with a sampling clock corresponding to the dot matrix counted by the counting circuit, by setting the display start position in the horizontal direction and the vertical direction, Has a larger number of display pixels than the number of display pixels determined from the dot matrix A projection display device capable of displaying an arbitrary position of an input video signal. 2. A setting range of a display start position set by said setting means is a difference between a horizontal pixel number of said video signal and a horizontal pixel number of said dot matrix in a horizontal direction, and a vertical direction of said video signal in a vertical direction. 2. The projection display device according to claim 1, wherein the difference is the difference between the number of pixels and the number of pixels in the vertical direction of the dot matrix. 3. In a position where the displayed screen can be moved,
2. The projection display device according to claim 1, wherein a marker indicating a direction in which a display position of the video signal can be moved is displayed. 4. The sampling clock generating circuit is a PLL (Phase Lock Loop) circuit whose frequency division ratio can be set externally, and the frequency of the sampling clock can be set according to the number of display pixels of the input video signal. 2. The projection display device according to claim 1, wherein: 5. The projection display device according to claim 1, wherein the display device is an LCD (Liquid Crystal Display) having a memory function such as a TFT (Thin Film Transistor) type. 6. The projection display apparatus according to claim 1, further comprising a line memory for storing the sampled video signal for one scanning period and reading it at an original sampling rate of the display device. 7. The number of display pixels determined from the dot matrix is 800 × 600 pixels, and the video signal is
2. The projection display device according to claim 1, wherein the number of pixels is 4 × 768 pixels. 8. A display device, comprising: means for counting a horizontal synchronization signal in a vertical synchronization period of an input video signal, wherein the display is performed by detecting the number of display pixels of the video signal identified from the number of scanning lines of the video signal. The projection display device according to claim 1, wherein 9. The projection display device according to claim 1, further comprising a remote controller, wherein the display start position is set according to an input signal from the remote controller. 10. The projection display device according to claim 1, further comprising means for compressing the number of display pixels of the input video signal, so that the entire video signal is displayed on the display device. 11. The projection display apparatus according to claim 10, wherein the compression by said compression means is obtained by sampling said input video signal with a sampling clock inherent in said display device.