JPH1140596A - Semiconductor device - Google Patents

Abstract

[PROBLEMS] To increase the height of a bonding wire loop from the main surface of a semiconductor chip without causing a short between a bonding wire of a signal line and a bus bar lead. Further, the thickness of the sealing body on the main surface of the semiconductor chip is increased without changing the thickness of the package. In a semiconductor device of a LOC package, a first region of an inner lead portion and a bus bar lead are arranged on a main surface of a semiconductor chip, and a second region of the inner lead portion is formed on a main surface of the semiconductor chip. A portion disposed substantially parallel to the semiconductor chip main surface of the bus bar lead of the inner lead portion is brought closer to the semiconductor chip main surface, and is insulated on the second region of the inner lead portion. Wire bonding is performed without applying a coating material.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a LOC type semiconductor device, and more particularly, to a TSOP (Thin Small Outline Pack).
The present invention relates to a technology effective when applied to a thin package such as kage).

[0002]

2. Description of the Related Art Conventional LOC type semiconductor devices include, for example,
As described in JP-A-2-246125, a semiconductor chip having a circuit and a plurality of external terminals formed on a main surface of a semiconductor substrate, a signal inner lead (first area) and a shared inner lead (second area) Area: hereinafter referred to as a bus bar lead), a plurality of leads each having an inner lead part formed integrally with the inner lead part, and a first area of the external terminal and the inner lead part. A semiconductor chip, an inner lead portion, and a sealing body for sealing the bonding wire. The first region of the inner lead portion and the bus bar lead are connected to the semiconductor chip. And the bus bar leads are disposed substantially parallel to the main surface of the semiconductor chip.

When this LOC type semiconductor device is applied to a thin and small package (TSOP), an insulating coating material is applied on the bus bar lead because the bonding wire of the signal line and the bus bar lead come into contact and short-circuit. .

FIG. 11 shows a schematic configuration of the LOC semiconductor device. This LOC type semiconductor device has a semiconductor chip 1
On the main surface, the bus bar leads 3A coated with a plurality of signal lines for inner leads 3A ₁ and the insulating coating material 20 on the upper surface
_An inner lead portion 3A made of ₂ is fixed to the semiconductor chip 1 via an electrically insulating film 4 with an adhesive. The lead 3 is composed of the inner lead 3A and the outer lead 3B formed integrally. The bus bar leads 3A ₂ was coated inner lead portion 3A signal line inner leads 3A ₁ and the insulating coating material 20 on the upper surface of the disposed on the main surface of the semiconductor chip, the bus bar leads 3A _2, the semiconductor chip 1 It is arranged substantially parallel to the main surface.

The plurality of signal inner leads 3A ₁ and bus bar leads 3A ₂ and the semiconductor chip 1 are electrically connected by bonding wires 5 and are sealed with a mold resin (mold resin) 2A. The sealed thin package 2 is formed by separating the suspension leads 3C and the outer leads 3B from the lead frame.

[0006]

In the conventional thin small package (TSOP), the thickness of the mold resin 2A on the upper surface of the semiconductor chip 1 is SOJ (Small Outline J).
−lead Package), it is difficult to control the loop of the bonding wire 5 to be low. That is, when lowering the loop of the bonding wire 5, since the bus bar lead 3A ₂ and the bonding wires 5 are short-circuited, at present, a problem that must be an insulating coating material 20 is applied on the bus bar lead 3A ₂ is there were.

In addition, since the thickness of the mold resin (sealing body) 2A on the main surface of the semiconductor chip is reduced, cracks and the like occur, and there is a problem that reliability is deteriorated.

It is an object of the present invention to provide a technique capable of increasing the height of a bonding wire loop from a main surface of a semiconductor chip without causing a short between a bonding wire of a signal line and a bus bar lead.

Another object of the present invention is to provide a technique capable of increasing the thickness of the sealing body on the main surface of the semiconductor chip without changing the thickness of the package.

Another object of the present invention is to provide a technique capable of reducing the cost of a bus bar lead frame.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, typical ones are briefly described as follows.

(1) A semiconductor chip having a circuit and a plurality of external terminals formed on a main surface of a semiconductor substrate, an inner lead portion having a first region and a second region, and integrally formed with the inner lead portion. A plurality of leads each having an outer lead portion, a bonding wire for electrically connecting the external terminal to the first region of the inner lead portion, and a semiconductor chip, an inner lead portion, and a bonding wire. A first region and a second region of the inner lead portion are disposed on a main surface of the semiconductor chip, and a second region of the inner lead portion is It is disposed substantially parallel to the main surface of the semiconductor chip, and is wire-bonded without applying an insulating coating material on the second region of the inner lead portion.

(2) In the semiconductor device of (1),
A portion of the second region of the inner lead portion disposed substantially parallel to the main surface of the semiconductor chip is bent toward the main surface of the semiconductor chip to approach the main surface of the semiconductor chip. Wire-bonded without applying an insulating coating material to the substrate.

(3) The height of a portion of the second region of the inner lead portion disposed substantially parallel to the main surface of the semiconductor chip is lower than the height of the first region of the inner lead portion. Wire bonding is performed without applying an insulating coating material on the second region of the inner lead portion.

(4) The tip of the first area of the inner lead portion to be wire-bonded has the same height as the second area, and the other portion of the first area is higher than the second area. In this case, wire bonding is performed on the region 2 without applying an insulating coating material.

According to the above-described means, the height of the bonding wire loop from the main surface of the semiconductor chip can be increased without shorting the bonding wire of the signal line and the bus bar lead, so that the thickness of the package is not changed. Thus, the thickness of the sealing body on the semiconductor chip can be increased.

Also, since the bonding wire of the signal line and the bus bar lead can be wire-bonded without short-circuiting without providing an insulating film on the bus bar lead of the inner lead portion, the cost of the bus bar lead frame can be reduced. .

Hereinafter, the present invention will be described in detail along with embodiments with reference to the drawings.

In all the drawings for explaining the embodiments of the present invention, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

[0021]

(Embodiment 1) FIG. 1 is a schematic diagram showing a schematic configuration of a semiconductor device according to Embodiment 1 of the present invention, and FIG. 2 is a plan view, a sectional view, and a view of a main part of FIG. FIG. 3 is an enlarged sectional view of a main part of the semiconductor device according to the first embodiment. In FIG. 2, (a) is a plan view, (b) is A-
FIG. 3C is a cross-sectional view taken along line A ′, FIG. 3C is a cross-sectional view taken along line BB ′ in FIG. 3A, and FIG. 3D is a cross-sectional view taken along line CC ′ in FIG. .

In all the embodiments of the present invention, the semiconductor chip is sealed with a TSOP type resin sealing type package. As shown in FIG. 1, this type of resin-sealed package employs a LOC (Lead On Chip) structure in which an inner lead portion is disposed on a rectangular semiconductor chip 1.

The inner lead 3A has one end integrally formed with the outer lead 3B. Signals to be applied to the outer lead portions 3B are defined and numbered based on the standard. In FIG. 1, the upper left end is the No. 1 terminal, and the lower left end is the No. 16 terminal. 17 below right
The terminal No. 32 and the upper right end are the terminal No. 32. That is, the present resin-encapsulated package has 32 terminals.

The first terminal, the seventh terminal, and the sixteenth terminal are power supply voltage Vcc terminals.
Volts (V) or 3 volts (V). 17th terminal,
The 27th terminal and the 32nd terminal are reference voltage Vss terminals, for example, 0 volt (V).

As shown in FIGS. 1 and 2, the inner lead portion 3A includes a plurality of signal line inner leads (first
Region) 3A ₁ and two bus bar lead (which is from the second region) 3A _2. It said plurality of signal lines for inner leads 3A ₁ traverses a rectangular respective long sides of the semiconductor chip 1, extends toward the center of the semiconductor chip 1, is a tip portion, shown in FIG. 2 (c) As shown in FIG. 3, the semiconductor chip 1 is disposed on the main surface of the semiconductor chip 1 with an insulating film 4 interposed therebetween. These distal end portion of each of a plurality of signal lines inner lead portion 3A ₁ is a bonding pad arranged in the central portion of each semiconductor chip 1 (external terminal)
Are connected by a bonding wire 5.

The two bus bar leads 3A ₂ are disposed substantially parallel to the main surface of the semiconductor chip 1. This bus bar lead portion 3A _2, as shown in FIGS. 2 and 3, is disposed in the main surface substantially parallel semiconductor chip 1,
The tip of the bus bar leads 3A close the portion 3A ₂₁ which are arranged parallel to the _two on the main surface of the semiconductor chip 1 than the support portion 3A ₂₂ of the bus bar lead portion 3A _2, the inner lead portions 3A ₁ for its height and the signal line and changing the height of the parts 3A _11.

As shown in FIG. 2D, the support portion 3A ₂₂ of the bus bar lead portion 3A ₂ is fixed to the main surface of the semiconductor chip 1 with an adhesive via an insulating film 4. Wherein said inner lead portions 3A ₁₁ in the region of the bus bar lead portion 3A ₂ without providing the insulating film and the semiconductor chip 1
Are bonded by wire bonding. The semiconductor chip, the inner leads 3A, and the bonding wires 5 are sealed with a mold resin (sealing body) 2A. The sealed thin package 2 is formed by separating the suspension leads 3C and the outer leads 3B from the lead frame.

A gold wire is used as the bonding wire. Instead of a gold wire, an aminium wire, a copper wire, or a coated wire in which an insulating resin is coated on the surface of a metal wire may be used.

As shown in FIG. 3 (the unit is millimeter: mm), the thickness of the semiconductor device according to the first embodiment is 1.0 mm. Mold resin (sealed body) 2 above the main surface of semiconductor chip 1
The thickness of A is 0.5 mm, and the thickness of the bonding wire 5
The thickness of the sealing body (mold resin) 2A from
It is at least 07 mm (minimum value 0.07 mm). The thickness of the semiconductor chip 1 is 0.28 mm, and the portion 3A _{2 1 of the} bus bar lead 3A ₂ arranged in parallel with the main surface of the semiconductor chip ₁
Is 0.125 mm, the thickness of the signal inner lead 3A ₁ is 0.125 mm, and the thickness of the insulating film 4 is 0.025 mm.
85 mm.

FIG. 4 shows a schematic configuration and dimensions of a main part of a conventional semiconductor device. The thickness of the semiconductor device is 1.0 mm, and a sealing body (mold resin) above the main surface of the semiconductor chip 1
The thickness of 2A is 0.40 mm, and the thickness of the mold resin (sealing body) 2A above the bonding wire 5 is:
It is 0.07 mm or more (minimum value 0.07 mm). The thickness of the semiconductor chip 1 is 0.28 mm, the thickness of the bus bar leads A ₂ is 0.125 mm, the thickness of the signal inner leads 3A ₁ 0.125 mm, the thickness of the insulating film 4 0.085
mm. Insulation coat on the bus bar leads 3A ₂ material 2
The thickness of 0 is 0.001 mm or more.

According to the present embodiment 1, as it can be seen from FIG. 3 and FIG. 4, a high bonding wire loop from the main surface of the semiconductor chip 1 without short bonding wires 5 and the bus bar lead 3A ₂ of the signal line Can be higher. Thereby, the thickness of the sealing body on the semiconductor chip 1 can be increased without changing the thickness of the package.

Further, without applying an insulating coating material (bus bar lead coating material) on the bus bar leads 3A ₂ of the inner leads 3A, wire bonding can be performed without short-circuiting the signal wire bonding wire 5 and the bus bar leads 3A _2. Therefore, the cost of the bus bar lead frame can be reduced.

(Embodiment 2) FIG. 5 shows Embodiment 2 of the present invention.
FIG. 6 is a schematic diagram showing a schematic configuration of a semiconductor device according to the third embodiment.
FIG. 6 is a plan view and a sectional view of a main part of FIG. 6, (a) is a plan view, (b) is a cross-sectional view taken along line AA 'in (a), and (c) is a cross-sectional view taken along line BB' in (a). (D) is a sectional view taken along line CC ′ of (a).

As shown in FIGS. 5 and 6, the semiconductor device according to the second embodiment differs from the first embodiment in that the bus bar lead 3A ₂ of the inner lead portion 3A is substantially parallel to the main surface of the semiconductor chip 1. 3A located at
Close by folding a ₂₁ on the main surface side of the semiconductor chip 1, the wire bonding without applying the bus bar lead 3A ₂ parts 3A ₂₁ on an insulating coating material that is substantially parallel to the main surface of the semiconductor chip 1 It was done. With this configuration, it is possible to obtain the same functions and effects as those of the first embodiment.

(Embodiment 3) FIG. 7 shows Embodiment 3 of the present invention.
FIG. 8 is a schematic diagram showing a schematic configuration of a semiconductor device according to the third embodiment.
FIG. 8 is a plan view and a sectional view of a main part of FIG. 8A is a plan view, FIG. 8B is a cross-sectional view taken along line AA ′ in FIG. 8A, and FIG. 8C is a cross-sectional view taken along line BB ′ in FIG. (D) is a sectional view taken along line CC ′ of (a).

As shown in FIGS. 7 and 8, the semiconductor device according to the third embodiment differs from the first embodiment in that the bus bar lead 3A ₂ of the inner lead portion 3A is substantially parallel to the main surface of the semiconductor chip 1. 3A located at
₂₁ was lower than the height of the signal inner leads 3A ₁ of the inner lead portion 3A (the thickness is thin), and is substantially parallel to the main surface of the semiconductor chip 1 on the bus bar leads 3A ₂ it is obtained by wire bonding without applying an insulating coating material on the portions 3A _21. With this configuration, it is possible to obtain the same functions and effects as those of the first embodiment.

(Embodiment 4) FIG. 9 shows Embodiment 3 of the present invention.
FIG. 1 is a schematic diagram showing a schematic configuration of a semiconductor device according to the first embodiment;
0 is a plan view and a sectional view of a main part of FIG. 10A is a plan view, FIG. 10B is a cross-sectional view taken along line AA ′ in FIG. 10A, and FIG. 10C is a cross-sectional view taken along line BB ′ in FIG. (D) is a sectional view taken along line CC ′ of (a).

The semiconductor device according to the fourth embodiment, as shown in FIGS. 9 and 10, in the embodiment 1, the distal portion 3A ₁₁ are wire bonding the inner lead portion 3A of the signal inner leads 3A ₁ High flush Satoshi and the bus bar leads 3A ₂ a is, other portions of the inner leads 3A ₁ for the signal is higher, is arranged substantially parallel to the main surface of the busbar semiconductor chip 1 on lead 3A ₂ on it are part 3A ₂₁ is obtained by wire bonding without applying an insulating coating material. With this configuration, it is possible to obtain the same functions and effects as those of the first embodiment.

As described above, the invention made by the present inventor is:
Although specifically described based on the embodiment, the present invention
It is needless to say that the present invention is not limited to the above-described embodiment, but can be variously modified without departing from the scope of the invention.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, the height of the bonding wire loop from the main surface of the semiconductor chip can be increased without shorting the bonding wire of the signal line and the bus bar lead, so that the thickness of the package is not changed. The thickness of the sealing body on the semiconductor chip can be increased.

Further, the wire bonding can be performed without short-circuiting the bonding wire of the signal line and the bus bar lead without applying an insulating coating material on the bus bar lead of the inner lead portion, so that the cost of the bus bar lead frame can be reduced. it can.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a schematic configuration of a lead frame of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view and a cross-sectional view of a main part of FIG.

FIG. 3 is an enlarged sectional view of a main part of the semiconductor device according to the first embodiment;

FIG. 4 is a diagram showing a schematic configuration and main dimensions of a main part of a conventional semiconductor device.

FIG. 5 is a schematic diagram showing a schematic configuration of a lead frame of a semiconductor device according to a second embodiment of the present invention.

6A and 6B are a plan view and a sectional view of a main part of FIG.

FIG. 7 is a schematic diagram showing a schematic configuration of a lead frame of a semiconductor device according to a third embodiment of the present invention.

8A and 8B are a plan view and a sectional view of a main part of FIG.

FIG. 9 is a schematic diagram showing a schematic configuration of a lead frame of a semiconductor device according to a third embodiment of the present invention.

FIG. 10 is a plan view and a cross-sectional view of a main part of FIG. 9;

FIG. 11 is a diagram showing a schematic configuration of a conventional LOC semiconductor device.

[Explanation of symbols]

1 ... semiconductor chip, 2 ... package, 2A ... mold resin (mold resin) 3 ... lead frame, 3A ₁ ... signal line for an inner lead, the distal end portion of 3A ₁₁ ... signal line inner leads, 3A ₂ ... bus bar leads, 3A ₂₁ : a portion of the bus bar lead arranged in parallel with the main surface of the semiconductor chip; 3A ₂₂ : a support portion of the bus bar lead; 4, an insulating film; 5, a bonding wire;

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Michiaki Sugiyama 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Nikkachi SLS Engineering Co., Ltd. (72) Inventor Masachika Masuda Kodaira, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (4)

[Claims] 1. A semiconductor chip having a circuit and a plurality of external terminals formed on a main surface of a semiconductor substrate, an inner lead having a first region and a second region, and an inner lead formed integrally with the inner lead. A plurality of leads each having an outer lead portion, a bonding wire for electrically connecting the external terminal to the first region of the inner lead portion, and the semiconductor chip, the inner lead portion, and the bonding wire are sealed. A first region and a second region of the inner lead portion are disposed on a main surface of the semiconductor chip, and a second region of the inner lead portion is formed of a semiconductor. A semi-conductor arranged substantially parallel to the chip main surface and wire-bonded to the second region of the inner lead without applying an insulating coating material. Body device. 2. A portion of the second region of the inner lead portion, which is disposed substantially in parallel with the main surface of the semiconductor chip, is bent toward the main surface of the semiconductor chip to approach the main surface of the semiconductor chip. 2. The semiconductor device according to claim 1, wherein the second region is wire-bonded without applying an insulating coating material. 3. A height of a portion of the second region of the inner lead portion disposed substantially in parallel with the main surface of the semiconductor chip is lower than a height of the first region of the inner lead portion. A semiconductor device wherein wire bonding is performed without applying an insulating coating material on a second region of a lead portion. 4. A front end of the inner lead portion to be wire-bonded in a first region has the same height as the second region, and the other portion of the first region is higher than the second region. A semiconductor device which is wire-bonded without applying an insulating coating material on the region of (1).