JPH1140601A - Structure of semiconductor device - Google Patents

Structure of semiconductor device

Info

Publication number
JPH1140601A
JPH1140601A JP9195560A JP19556097A JPH1140601A JP H1140601 A JPH1140601 A JP H1140601A JP 9195560 A JP9195560 A JP 9195560A JP 19556097 A JP19556097 A JP 19556097A JP H1140601 A JPH1140601 A JP H1140601A
Authority
JP
Japan
Prior art keywords
chip
electrode pad
wire
wire bonding
barrier metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9195560A
Other languages
Japanese (ja)
Other versions
JP3555062B2 (en
Inventor
Kazutaka Shibata
和孝 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP19556097A priority Critical patent/JP3555062B2/en
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to EP98900725A priority patent/EP0890989A4/en
Priority to KR10-2004-7000090A priority patent/KR100467946B1/en
Priority to US09/155,134 priority patent/US6133637A/en
Priority to PCT/JP1998/000281 priority patent/WO1998033217A1/en
Priority to KR10-1998-0707403A priority patent/KR100522223B1/en
Publication of JPH1140601A publication Critical patent/JPH1140601A/en
Priority to US09/612,480 priority patent/US6458609B1/en
Application granted granted Critical
Publication of JP3555062B2 publication Critical patent/JP3555062B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07541—Controlling the environment, e.g. atmosphere composition or temperature
    • H10W72/07551—Controlling the environment, e.g. atmosphere composition or temperature characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 ＩＣチップ２の表面に、保護膜を、当該表面
におけるワイヤボンディング用電極パッド２ｃの部分に
開口部を設けて形成し、前記電極パッド２ｃの部分に、
バリアメタル２ｅを形成して成る半導体装置において、
前記ワイヤボンディング用電極パッド２ｃに対して金属
ワイヤ５を接合することが確実・強固にできるようにす
る。 【手段】 前記バリアメタル２ｅの表面に、薄い金層２
ｅ′を形成し、この金層２ｅ′に対して金属ワイヤ５を
ボール接合する。 (57) Abstract: A protective film is formed on a surface of an IC chip 2 by providing an opening at a portion of a wire bonding electrode pad 2c on the surface, and a protective film is formed on the electrode pad 2c.
In a semiconductor device formed by forming a barrier metal 2e,
The metal wire 5 can be reliably and firmly bonded to the wire bonding electrode pad 2c. A thin gold layer is formed on the surface of the barrier metal.
e 'is formed, and the metal wire 5 is ball-bonded to the gold layer 2e'.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＩＣチップの表面
に、各種の回路素子を形成すると共に、この回路素子に
対するワイヤボンディング用電極パッドを形成して成る
半導体装置の構造に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device in which various circuit elements are formed on the surface of an IC chip and an electrode pad for wire bonding to the circuit element is formed.

【０００２】[0002]

【従来の技術】一般、この種の半導体装置では、前記Ｉ
Ｃチップの表面に形成するワイヤボンディング用電極パ
ッドをアルミニウム製にする一方、前記ＩＣチップの表
面に、当該表面に形成されている各種の回路素子を覆う
絶縁体による保護膜を、前記ワイヤボンディング用電極
パッドの部分に開口部を設けて形成し、前記ワイヤボン
ディング用電極パッドのうち前記保護膜の開口部内の部
分に対して、外部との接続用金属ワイヤをボール接合
（ワイヤボンディング）するように構成しているが、こ
の構造では、金等の金属ワイヤを電極パッドに対してボ
ール接合するときの衝撃等にて、電極パッド及び保護膜
を損傷するおそれが大きいのであった。2. Description of the Related Art Generally, in this type of semiconductor device, the I
A wire bonding electrode pad formed on the surface of the C chip is made of aluminum, and a protective film made of an insulator covering various circuit elements formed on the surface of the IC chip is formed on the surface of the IC chip. An opening is formed in the electrode pad portion, and a metal wire for connection to the outside is ball-bonded (wire-bonded) to a portion of the wire bonding electrode pad inside the opening of the protective film. However, in this structure, there is a high possibility that the electrode pad and the protective film are damaged by an impact or the like when a metal wire such as gold is bonded to the electrode pad with a ball.

【０００３】そこで、最近の半導体装置においては、例
えば、特開平３−２２７５３９号公報等に記載されてい
るように、前記ワイヤボンディング用電極パッドの部分
に、バリアメタルを、当該電極パッドのうち前記保護膜
の開口部内の部分及び保護膜のうち開口部の周囲縁の部
分を覆うように形成し、このバリアメタルの表面に対し
て、金属ワイヤをボール接合するようにしている。Therefore, in a recent semiconductor device, as described in, for example, Japanese Patent Application Laid-Open No. 3-227538, a barrier metal is provided on the wire bonding electrode pad, The protective film is formed so as to cover the portion inside the opening and the portion of the protective film around the opening, and the metal wire is ball-bonded to the surface of the barrier metal.

【０００４】[0004]

【発明が解決しようとする課題】しかし、このように、
ワイヤボンディング用電極パッドの部分に、バリアメタ
ルを形成して、このバリアメタルの表面に対して、金属
ワイヤをボール接合することは、そのボール接合の際に
発生する電極パッド及び保護膜の損傷を、前記バリアメ
タルにて低減することができるものの、このバリアメタ
ルをアルミニウム製電極パッドの表面に形成すると、こ
の電極パッドに対する金等の金属ワイヤの接合性が低下
するから、その接合に接合強度の低下等の接合不良が発
生することのおそれが大きくなり、半導体装置における
ワイヤボンディングに際しての不良率が高くなると言う
問題があった。However, as described above,
Forming a barrier metal on the portion of the electrode pad for wire bonding and ball-joining the metal wire to the surface of the barrier metal prevents damage to the electrode pad and the protective film that occur at the time of the ball joining. Although it can be reduced by the barrier metal, if the barrier metal is formed on the surface of the aluminum electrode pad, the bondability of a metal wire such as gold to the electrode pad is reduced. There has been a problem that the possibility of occurrence of bonding failures such as reduction increases, and the failure rate at the time of wire bonding in a semiconductor device increases.

【０００５】本発明は、この問題を解消することを技術
的課題とするものである。An object of the present invention is to solve this problem.

【０００６】[0006]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「ＩＣチップの表面に、当該表面に形
成されている各種の回路素子を覆う保護膜を、当該表面
に形成されているワイヤボンディング用電極パッドの部
分に開口部を設けて形成し、更に、前記ワイヤボンディ
ング用電極パッドの部分に、バリアメタルを形成して成
る半導体装置において、前記バリアメタルの表面に、薄
い金層を形成し、この金層に対して金属ワイヤをワイヤ
ボンディングする。」と言う構成にした。In order to achieve the above technical object, the present invention provides a method of forming a protective film on a surface of an IC chip, which covers various circuit elements formed on the surface. In the semiconductor device, an opening is provided at a portion of the electrode pad for wire bonding, and a barrier metal is formed at the portion of the electrode pad for wire bonding. A layer is formed, and a metal wire is wire-bonded to the gold layer. "

【０００７】[0007]

【発明の作用・効果】このように、ワイヤボンディング
用電極パッドに対するバリアメタルの表面に、薄い金層
を形成することにより、金属ワイヤをバリアメタルに対
してワイヤボンディングするときにおいて、前記薄い金
層が、バリアメタル及び金属ワイヤの両方に対して合金
化することになるから、金属ワイヤのバリアメタルに対
する接合性を確実に向上できるのである。As described above, by forming a thin gold layer on the surface of the barrier metal for the electrode pad for wire bonding, the thin gold layer is formed when the metal wire is wire-bonded to the barrier metal. However, since the alloy is formed into both the barrier metal and the metal wire, the bondability of the metal wire to the barrier metal can be surely improved.

【０００８】従って、本発明によると、半導体装置に対
するワイヤボンディングに際して、その金属ワイヤを電
極パッドに対し確実、且つ、強固にワイヤボンディング
することができるから、半導体装置におけるワイヤボン
ディングに際しての不良率を大幅に低減できる効果を有
する。特に、請求項２に記載したように、バリアメタル
を、電極パッドのうち前記保護膜の開口部内の部分及び
保護膜のうち開口部の周囲縁の部分を覆うように形成す
ることにより、このバリアメタルにて保護膜を押さえる
ことができるから、前記の効果をより助長できる。Therefore, according to the present invention, when wire bonding to a semiconductor device, the metal wire can be securely and firmly wire-bonded to the electrode pad. It has the effect of being able to be reduced. In particular, as described in claim 2, the barrier metal is formed so as to cover a portion of the electrode pad inside the opening of the protective film and a portion of the protective film around the opening around the opening. Since the protective film can be held down by metal, the above effect can be further promoted.

【０００９】[0009]

【発明の実施の形態】以下、本発明の実施の形態を、二
つのＩＣチップを使用した半導体装置に適用した場合の
図面（図１〜図８）について説明する。この図において
符号１は、矩形状のチップマウント部１ａと、このチッ
プマウント部１ａにおける四つの各辺から外向きに延び
る複数本のリード端子１ｂとを備えたリードフレームを
示す。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will now be given of drawings (FIGS. 1 to 8) in which an embodiment of the present invention is applied to a semiconductor device using two IC chips. In this drawing, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.

【００１０】また、符号２は、前記リードフレーム１に
おけるチップマウント部１ａの上面にマウントされるメ
インＩＣチップを示し、このメインＩＣチップ２の上面
には、図示しない能動素子又は受動素子等のような回路
素子の多数個が形成されていると共に、その周囲にワイ
ヤボンディング用電極パッド２ｃの多数個が、その内側
に後述するサブＩＣチップ３に対する接続用の電極パッ
ド２ａの多数個が各々形成されている。Reference numeral 2 denotes a main IC chip mounted on the upper surface of the chip mounting portion 1a of the lead frame 1. The upper surface of the main IC chip 2 is provided with an active element or a passive element (not shown). And a plurality of electrode pads 2c for wire bonding are formed around it, and a plurality of electrode pads 2a for connection to a sub IC chip 3 described later are formed inside the plurality of circuit elements. ing.

【００１１】更に、このメインＩＣチップの上面には、
図３に示すように、当該上面に形成されている各種の回
路素子を覆う保護膜２ｄが、前記各ワイヤボンディング
用電極パッド２ｃの部分に開口部を設けて形成されてい
る。加えて、前記各ワイヤボンディング用電極パッド２
ｃの部分には、パリアメタル２ｅが、当該電極パッド２
ｃのうち前記保護膜２ｄの開口部内の部分及び前記保護
膜２ｄのうち開口部の周囲縁の部分を覆うように形成さ
れている。なお、このバリアメタル２ｅは、例えば、チ
タンを下層としタングステンを上層とするか、クロム下
層とし銀を上層とする二層構造に構成されている。Further, on the upper surface of the main IC chip,
As shown in FIG. 3, a protective film 2d for covering various circuit elements formed on the upper surface is formed by providing an opening at each of the wire bonding electrode pads 2c. In addition, each of the wire bonding electrode pads 2
In the portion of c, the metal pad 2e is
The protective film 2d is formed so as to cover a portion inside the opening of the protective film 2d and a portion of the protective film 2d around the opening. The barrier metal 2e has, for example, a two-layer structure including titanium as a lower layer and tungsten as an upper layer, or chromium as a lower layer and silver as an upper layer.

【００１２】一方、符号３は、前記メインＩＣチップ２
の上面にマウントされるサブＩＣチップを示し、このサ
ブＩＣチップ３における表裏両面のうち片面には、前記
メインＩＣチップ２と同様に図示しない能動素子又は受
動素子等のような回路素子の多数個が形成されていると
共に、前記メインＩＣチップ２の上面における各電極パ
ッド２ｂの各々に対応する箇所ごとに接続用の電極パッ
ド３ａが形成されている。On the other hand, reference numeral 3 denotes the main IC chip 2
A sub IC chip mounted on the upper surface of the sub IC chip 3. On one of the front and back surfaces of the sub IC chip 3, a large number of circuit elements such as active elements or passive elements (not shown) similar to the main IC chip 2 are shown. Are formed, and connection electrode pads 3a are formed at locations corresponding to the respective electrode pads 2b on the upper surface of the main IC chip 2.

【００１３】そして、前記メインＩＣチップ２における
各電極パッド２ａ、及び前記サブＩＣチップ３における
各電極パッド３ａの各々に、金又は半田によるパンプ２
ｂ，３ｂを設ける一方、前記サブＩＣチップ３を、図４
に示すように、その回路素子及び電極パッド３ａを形成
した面を下向きにして、前記メインＩＣチップ２の上面
側に、当該サブＩＣチップ３の各電極パッド３ａにおけ
るバンプ３ｂの各々が、メインＩＣチップ２の各電極バ
ンプ２ｂにおけるバンプ２ｂの各々に接当するように載
置したのち、全体を加熱しながら、サブＩＣチップ３を
メインＩＣチップ２に対して押圧（この押圧と同時に超
音波を振動を付与しても良い）することにより、互いに
接当するバンプ２ｂ，３ｂを電気的に接合すると共に、
前記メインＩＣチップ２の上面と、前記サブＩＣチップ
３の下面との間の隙間に、エポキシ樹脂等の合成樹脂に
よる接着剤４又はエラストマーを充填して、両ＩＣチッ
プ２，３を一体化する。Each of the electrode pads 2a of the main IC chip 2 and each of the electrode pads 3a of the sub IC chip 3 is provided with a pump 2 made of gold or solder.
b and 3b, while the sub IC chip 3 is
As shown in FIG. 2, the bumps 3b of the respective electrode pads 3a of the sub IC chip 3 are provided on the upper surface side of the main IC chip 2 with the surface on which the circuit elements and the electrode pads 3a are formed face down. After placing each of the bumps 2b on each of the electrode bumps 2b of the chip 2 so as to be in contact therewith, the sub IC chip 3 is pressed against the main IC chip 2 while heating the whole (ultrasonic wave is applied simultaneously with this pressing). (Vibration may be applied), thereby electrically connecting the bumps 2b and 3b which are in contact with each other,
A gap between the upper surface of the main IC chip 2 and the lower surface of the sub IC chip 3 is filled with an adhesive 4 or an elastomer made of a synthetic resin such as an epoxy resin to integrate the two IC chips 2 and 3. .

【００１４】次いで、これらの全体を、図５に示すよう
に、前記リードフレーム１におけるチップマウント部１
ａの上面に、前記メインＩＣチップ２を接着剤等にて固
着するようにしてマウントしたのち、前記メインＩＣチ
ップ２の上面における各ワイヤボンディング用電極パッ
ド２ｃと、リードフレーム１における各リード端子１ｂ
との間を、細い金等の金属ワイヤ５によるワイヤボンデ
ィングにて電気的に接続するのである。Next, as shown in FIG. 5, the whole of these is mounted on the chip mount portion 1 of the lead frame 1.
a, the main IC chip 2 is mounted on the upper surface of the main IC chip 2 so as to be fixed thereto by an adhesive or the like, and each of the wire bonding electrode pads 2c on the upper surface of the main IC chip 2 and each of the lead terminals 1b on the lead frame 1.
Are electrically connected by wire bonding with a thin metal wire 5 such as gold.

【００１５】このワイヤボンディングに先立って、前記
各ワイヤボンディング用電極パッド２ｃの部分における
バリアメタル２ｅの表面に、予め薄い金層２ｅ′を、金
のフラッシュメッキにて形成しておき、これに対して、
図６に示すように、前記金属ワイヤ５に一端的に形成し
たボール部５ａを押圧することにより接合するのであっ
て、前記金属ワイヤ５を電極パッド２ｃにおけるバリア
メタル２ｅに対してボール接合するときにおいて、前記
薄い金層２ｅ′が、バリアメタル２ｅ及び金属ワイヤ５
の両方に対して合金化することになるから、金属ワイヤ
５のバリアメタル２ｅに対する接合性を確実に向上でき
るのである。Prior to the wire bonding, a thin gold layer 2e 'is formed in advance on the surface of the barrier metal 2e at each of the wire bonding electrode pads 2c by flash plating with gold. hand,
As shown in FIG. 6, when bonding is performed by pressing a ball portion 5a formed at one end to the metal wire 5, when the metal wire 5 is ball-bonded to the barrier metal 2e in the electrode pad 2c. In the above, the thin gold layer 2e 'comprises a barrier metal 2e and a metal wire 5e.
Therefore, the bonding property of the metal wire 5 to the barrier metal 2e can be surely improved.

【００１６】このようにして、一体化した二つのＩＣチ
ップ２，３を、リードフレーム１にマウントしたのち、
メインＩＣチップ２における各ワイヤボンディング用電
極パッド２ｃとリードフレーム１における各リード端子
１ｂとの間を金属ワイヤ５にてワイヤボンディングする
と、図７に示すように、全体を密封する合成樹脂製のパ
ッケージ部６を、トランスファ成形によって成形し、次
いで、図８に示すように、リードフレーム１から切り放
したのち、各リード端子１ｂのうちパッケージ部６から
突出する部分を、パッケージ部６の下面と略同一平面状
になるように折り曲げすることにより、パッケージ型半
導体装置の完成品とするのである。After mounting the two integrated IC chips 2 and 3 on the lead frame 1 in this manner,
When wire bonding is performed between each of the wire bonding electrode pads 2c of the main IC chip 2 and each of the lead terminals 1b of the lead frame 1 with a metal wire 5, as shown in FIG. After the portion 6 is formed by transfer molding, and then cut off from the lead frame 1 as shown in FIG. 8, the portion of each lead terminal 1b projecting from the package portion 6 is substantially the same as the lower surface of the package portion 6. By folding the semiconductor device into a planar shape, a packaged semiconductor device is completed.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施形態を示す分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of the present invention.

【図２】図１の縦断正面図である。FIG. 2 is a vertical sectional front view of FIG.

【図３】図２の要部拡大図である。FIG. 3 is an enlarged view of a main part of FIG. 2;

【図４】前記実施形態においてメインＩＣチップに対し
てサブＩＣチップを一体化した状態を示す縦断正面図で
ある。FIG. 4 is a longitudinal sectional front view showing a state where a sub IC chip is integrated with a main IC chip in the embodiment.

【図５】前記実施形態においてサブＩＣチップをマウン
トしたメインＩＣチップをリードフレームに対してマウ
ントした状態を示す縦断正面図である。FIG. 5 is a longitudinal sectional front view showing a state where a main IC chip on which a sub IC chip is mounted in the embodiment is mounted on a lead frame;

【図６】図５の要部拡大図である。FIG. 6 is an enlarged view of a main part of FIG. 5;

【図７】前記実施形態において全体を密封するパッケー
ジ部を成形した状態を示す縦断正面図である。FIG. 7 is a longitudinal sectional front view showing a state in which a package portion for sealing the whole is molded in the embodiment.

【図８】前記実施形態における半導体装置の縦断正面図
である。FIG. 8 is a vertical sectional front view of the semiconductor device in the embodiment.

【符号の説明】[Explanation of symbols]

１ リードフレーム １ａ チップマウント部 １ｂ リード端子 ２ メインＩＣチップ ２ａ 電極パッド ２ｂ バンプ ２ｃ ワイヤボンディング用電極パ
ッド ２ｄ 保護膜 ２ｅ バリアメタル ２ｅ′ 金層 ３ サブＩＣチップ ３ａ 電極パッド ３ｂ バンプ ４ 合成樹脂の接着剤 ５ 金属線 ６ パッケージ部DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 Main IC chip 2a Electrode pad 2b Bump 2c Wire bonding electrode pad 2d Protective film 2e Barrier metal 2e 'Gold layer 3 Sub IC chip 3a Electrode pad 3b Bump 4 Synthetic resin adhesive 5 Metal wire 6 Package part

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】ＩＣチップの表面に、当該表面に形成され
ている各種の回路素子を覆う保護膜を、当該表面に形成
されているワイヤボンディング用電極パッドの部分に開
口部を設けて形成し、更に、前記ワイヤボンディング用
電極パッドの部分に、バリアメタルを形成して成る半導
体装置において、 前記バリアメタルの表面に、薄い金層を形成し、この金
層に対して金属ワイヤをワイヤボンディングすることを
特徴とする半導体装置の構造。1. A protective film for covering various circuit elements formed on a surface of an IC chip by forming an opening in a portion of a wire bonding electrode pad formed on the surface. Further, in a semiconductor device having a barrier metal formed on a portion of the wire bonding electrode pad, a thin gold layer is formed on a surface of the barrier metal, and a metal wire is wire-bonded to the gold layer. A structure of a semiconductor device, characterized in that: 【請求項２】ＩＣチップの表面に、当該表面に形成され
ている各種の回路素子を覆う保護膜を、当該表面に形成
されているワイヤボンディング用電極パッドの部分に開
口部を設けて形成し、更に、前記ワイヤボンディング用
電極パッドの部分に、バリアメタルを、当該電極パッド
のうち前記保護膜の開口部内の部分及び保護膜のうち開
口部の周囲縁の部分を覆うように形成して成る半導体装
置において、 前記バリアメタルの表面に、薄い金層を形成し、この金
層に対して金属ワイヤをワイヤボンディングすることを
特徴とする半導体装置の構造。2. A protection film for covering various circuit elements formed on the surface of an IC chip by providing an opening at a portion of a wire bonding electrode pad formed on the surface. Further, a barrier metal is formed on the portion of the wire bonding electrode pad so as to cover a portion of the electrode pad inside the opening of the protection film and a portion of the protection film around the opening. In a semiconductor device, a thin gold layer is formed on a surface of the barrier metal, and a metal wire is wire-bonded to the gold layer.
JP19556097A 1997-01-24 1997-07-22 Structure of semiconductor device Expired - Lifetime JP3555062B2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP19556097A JP3555062B2 (en) 1997-07-22 1997-07-22 Structure of semiconductor device
KR10-2004-7000090A KR100467946B1 (en) 1997-01-24 1998-01-22 Method for manufacturing a semiconductor chip
US09/155,134 US6133637A (en) 1997-01-24 1998-01-22 Semiconductor device having a plurality of semiconductor chips
PCT/JP1998/000281 WO1998033217A1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
EP98900725A EP0890989A4 (en) 1997-01-24 1998-01-22 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE DEVICE
KR10-1998-0707403A KR100522223B1 (en) 1997-01-24 1998-01-22 Semiconductor device and method for manufacturing thereof
US09/612,480 US6458609B1 (en) 1997-01-24 2000-07-07 Semiconductor device and method for manufacturing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19556097A JP3555062B2 (en) 1997-07-22 1997-07-22 Structure of semiconductor device

Publications (2)

Publication Number Publication Date
JPH1140601A true JPH1140601A (en) 1999-02-12
JP3555062B2 JP3555062B2 (en) 2004-08-18

Family

ID=16343154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19556097A Expired - Lifetime JP3555062B2 (en) 1997-01-24 1997-07-22 Structure of semiconductor device

Country Status (1)

Country Link
JP (1) JP3555062B2 (en)

Cited By (7)

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Publication number Priority date Publication date Assignee Title
JP2002373910A (en) * 2000-09-12 2002-12-26 Rohm Co Ltd Semiconductor device
JP2003017656A (en) * 2001-07-04 2003-01-17 Matsushita Electric Ind Co Ltd Semiconductor package and semiconductor device using the same
US6744140B1 (en) 1999-09-20 2004-06-01 Rohm Co., Ltd. Semiconductor chip and method of producing the same
US6794732B2 (en) 2001-07-25 2004-09-21 Rohn Co., Ltd. Semiconductor device and method of manufacturing the same
JP2009170745A (en) * 2008-01-18 2009-07-30 Fujitsu Microelectronics Ltd Electronic equipment
US7759803B2 (en) 2001-07-25 2010-07-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6744140B1 (en) 1999-09-20 2004-06-01 Rohm Co., Ltd. Semiconductor chip and method of producing the same
KR100752885B1 (en) * 1999-09-20 2007-08-28 로무 가부시키가이샤 Semiconductor chip and method for manufacturing the same
JP2002373910A (en) * 2000-09-12 2002-12-26 Rohm Co Ltd Semiconductor device
JP2003017656A (en) * 2001-07-04 2003-01-17 Matsushita Electric Ind Co Ltd Semiconductor package and semiconductor device using the same
US6794732B2 (en) 2001-07-25 2004-09-21 Rohn Co., Ltd. Semiconductor device and method of manufacturing the same
US7244635B2 (en) 2001-07-25 2007-07-17 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
US7759803B2 (en) 2001-07-25 2010-07-20 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
US8049343B2 (en) 2001-07-25 2011-11-01 Rohm Co., Ltd. Semiconductor device and method of manufacturing the same
JP2009170745A (en) * 2008-01-18 2009-07-30 Fujitsu Microelectronics Ltd Electronic equipment
US8981574B2 (en) 2012-12-20 2015-03-17 Samsung Electronics Co., Ltd. Semiconductor package
US9633973B2 (en) 2012-12-20 2017-04-25 Samsung Electronics Co., Ltd. Semiconductor package

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