JPH1141101A - Digital data processing apparatus and method - Google Patents

Abstract

(57) [Summary] [Problem] It has been difficult to perform level control processing for effecting an effect such as a limiter by non-linear processing used in digital audio mastering or the like on 1-bit data. SOLUTION: An instantaneous peak value detector 3 detects an instantaneous peak value level A of an amplitude of a low-frequency component of a 1-bit data input X from a ΔΣ modulator 2. The gain generator 4 calculates the instantaneous peak level A detected by the instantaneous peak level detector 3.
A gain coefficient K is generated according to. The level controller 7 controls the level of the 1-bit data based on the gain coefficient K generated by the gain generator 4, and outputs a 1-bit data output Y subjected to a non-linear limiter process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data processing apparatus and method for controlling the level in the amplitude direction of 1-bit data obtained by subjecting an original audio signal to digital modulation.

[0002]

2. Description of the Related Art One-bit data obtained by subjecting an original analog audio signal to delta-sigma (.DELTA..SIGMA.) Modulation processing has, for example, a sampling frequency of 44.1 kHz.
For example, as compared with conventional digital audio data having a format of z and a data word length of 16 bits, for example, the sampling frequency is 64 times 44.1 kHz and the data word length is 1 bit.
Like bits, it has a very high sampling frequency and a short data word length, and features a wide transmittable frequency band. Further, even with 1-bit data by the ΔΣ modulation processing, a high dynamic range can be secured in an audio band that is low with respect to an oversampling frequency of 64 times. By utilizing this feature, it can be applied to high-quality sound recorders and data transmission.

The ΔΣ modulation circuit itself for performing the above delta sigma modulation processing on the analog audio signal is not particularly a new technology, the circuit configuration is suitable for integration, and the accuracy of A / D conversion can be obtained relatively easily. This is a circuit that has been widely used in an A / D converter and the like.

[0004] One-bit data obtained by ΔΣ modulation processing can be returned to an analog audio signal by passing through a simple analog low-pass filter.

On the other hand, it is difficult to perform a level control process on the 1-bit data to provide an effect effect such as a limiter by a non-linear process used in digital audio mastering or the like. For example, a level control process such as the non-linear process is performed on an analog signal obtained by once performing an analog conversion process on the 1-bit data, and then the data is converted into the 1-bit data again.

[0006]

By the way, the level control processing such as the non-linear processing is performed on the analog signal obtained by once performing the analog conversion processing on the 1-bit data, and then converted into the 1-bit data again. In this method, an analog non-linear device is required, and processing is performed on a signal that has already been converted to 1-bit data.
(4) Modulation must be performed, resulting in a complicated configuration and a decrease in signal quality.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a simple configuration in which the level of 1-bit data is changed according to the instantaneous peak value level of the amplitude of the low-frequency audio signal component of 1-bit data. It is another object of the present invention to provide a digital data processing device capable of controlling without deteriorating sound quality.

Further, the present invention has been made in view of the above-mentioned circumstances, and the level of the 1-bit data is made simple according to the average energy level of the amplitude of the low-frequency audio signal component of the 1-bit data. Another object of the present invention is to provide a digital data processing device capable of performing control without deteriorating sound quality.

Further, the present invention has been made in view of the above-mentioned circumstances, and the level of the 1-bit data is determined by a simple configuration according to the level information of the amplitude of the low-frequency audio signal component of the 1-bit data. It is another object of the present invention to provide a digital data processing method capable of controlling without deteriorating sound quality.

[0010]

In order to solve the above-mentioned problems, a digital data processing apparatus according to the present invention provides an instantaneous peak value level of the amplitude of a low-frequency component of 1-bit data detected by an instantaneous peak value level detecting means. , The gain generation means generates a gain coefficient, and the level control means controls the level of the 1-bit data based on the gain coefficient.

This digital data processing device includes delay means for delaying the one-bit data by a time corresponding to the processing time of the instantaneous peak value level detection means and the gain generation means. Above 1
The level of the bit data is controlled by the level control means.

Here, the gain generating means generates the gain coefficient based on a storing means storing a value derived from a transfer function of a predetermined input / output characteristic.

The operating frequencies of the instantaneous peak value level detecting means and the gain generating means may be lower than the clock frequency used in the delta-sigma modulation processing.

In order to solve the above-mentioned problem, the digital data processing apparatus according to the present invention is characterized in that the gain generation means has a function corresponding to the average energy level of the amplitude of the low-frequency component of the 1-bit data detected by the average energy level detection means. A gain coefficient is generated, and the level control means controls the level of the 1-bit data based on the gain coefficient.

This digital data processing device includes delay means for delaying the one-bit data by a time corresponding to the processing time of the average energy level detection means and the gain generation means, and the digital data processing apparatus is delayed by the delay means. The level of the 1-bit data is controlled by the level control means.

Here, the gain generation means generates the gain coefficient based on storage means storing a value derived from a transfer function of a predetermined input / output characteristic.

The operating frequencies of the average energy level detecting means and the gain generating means may be lower than the clock frequency used in the delta sigma modulation processing.

In order to solve the above-mentioned problems, the digital data processing method according to the present invention detects level information of the amplitude of a low-frequency component of 1-bit data, and generates a gain coefficient generated in accordance with the amplitude level information. Control the level of the 1-bit data based on

Here, the amplitude level information is an instantaneous peak value level of the amplitude of the low frequency component of the 1-bit data. The amplitude level information is an average energy level of a low-frequency component of the 1-bit data.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some embodiments of a digital data processing apparatus and method according to the present invention will be described below.

First, in the first embodiment, 1-bit data obtained by subjecting an original analog audio signal to a delta-sigma (ΔΣ) modulation process is subjected to a non-linear limiter process, the level is controlled, and the limiter process is performed. Is a 1-bit data processing device such as an effect device that outputs an audio signal to which is applied. This 1-bit data processing apparatus detects the level information of the amplitude of the low frequency component of the 1-bit data, and detects the 1-bit data based on the gain coefficient generated in accordance with the amplitude level information. By applying a digital data processing method characterized by controlling the level of bit data, the level of the 1-bit data can be changed with a simple configuration according to the level information of the amplitude of the low-frequency audio signal component of the 1-bit data. , And can be controlled without deteriorating the sound quality.

The 1-bit data processing apparatus shown in FIG. 1 performs amplitude modulation of a low-frequency component of a 1-bit data input X from a ΔΣ modulator 2 for performing ΔΣ modulation processing on an original analog audio signal supplied from an input terminal 1. And an instantaneous peak level detector 3 such as a digital FIR filter for detecting the instantaneous peak level A, and a gain coefficient K is generated according to the instantaneous peak level A detected by the instantaneous peak level detector 3. Gain generator 4 and gain generator 4
And a level controller 7 that controls the level of the 1-bit data based on the gain coefficient K generated in step (1) and outputs a 1-bit data output Y subjected to a non-linear limiter process.

The 1-bit data processing apparatus further includes a delay line 6 for delaying the 1-bit data by a time corresponding to the processing time of the instantaneous peak value level detector 3 and the gain generator 4. The level controller 7 controls the level of the 1-bit data delayed at 6.

The level controller 7 multiplies the delayed 1-bit data from the delay line 6 by the gain coefficient K from the gain generator 4 and outputs a multiplied output Z.
And a ΔΣ modulator 9 for subjecting the multiplied output Z from the multiplier 8 to Δ こ の modulation processing again.

The gain generator 4 reads a gain coefficient K corresponding to the instantaneous peak value level A from a ROM table 5 storing input / output characteristics obtained by a non-linear limiter function described later. The coefficient K is supplied to the multiplier 8 of the level controller 7.

Here, a detailed configuration of the Δ 構成 modulator 2 and the ΔΣ modulator 9 is shown in FIG. For example, the ΔΣ modulator 2 includes an adder 16, an integrator 17, a quantizer 18, a delay unit 2
0. The addition output of the adder 16 is an integrator 17
, And the integrated output from the integrator 17 is supplied to the quantizer 18.
Supplied to The quantized output of the quantizer 18 is output terminal 1
9 and a negative sign via the delay unit 20 and fed back to the adder 16 to be input to the input terminal 15
It is added to the analog audio signal supplied from the input terminal 1 (in FIG. 1, the input terminal 1). The added output from the adder 16 is integrated by an integrator 17, and the integrated output from the integrator 17 is quantized by a quantizer 18 into 1-bit data for each sample period.

Note that the ΔΣ modulators 2 and 9 are a normal PC
Sampling frequency fs used in M processing (= 44.1K
For example, a clock of 64 fs, which is 64 times the frequency (Hz), is used as the sampling clock. Each unit shown in FIG. 1 uses this 64 fs as a system clock, that is, an operating frequency.

In this one-bit data processing device, as described above, a non-linear limiter process is performed on one-bit data. FIG. 3 shows this nonlinear limiter processing characteristic.

The nonlinear limiter processing characteristic shown in FIG. 3, y = f (x) (1) is a conventional multi-bit PCM having a configuration as shown in FIG.
It was only possible by the device. In FIG. 4, a PCM signal input x from an input terminal 25 is converted into an output signal y subjected to a non-linear limiter process according to the input signal level by a converter 26 that performs level conversion by an input / output function f (x). You. The converted output y is derived from the output terminal 27. As described above, in the multi-bit PCM, since the input signal x itself represents the amplitude value of the signal, the processing output value can be directly determined by the input / output function.

On the other hand, in the case of the 1-bit data, the data itself has only two maximum and minimum amplitude values consisting of "0" and "1", and a processing signal is directly obtained from a 1-bit data input by an input / output function. I couldn't do that.

In the 1-bit data processing apparatus shown in FIG. 1, the instantaneous peak value level detector 3 detects the instantaneous peak value level of the low-frequency audio signal component from the 1-bit data input. , The gain generator 4 generates a conversion gain coefficient. Then, based on the gain coefficient, the level controller 7 obtains 1-bit data whose level is controlled, that is, 1-bit data output subjected to nonlinear limit processing.

The operation of the 1-bit data processing device will be described in detail with reference to the timing chart of FIG. First, an original analog audio signal ((a) in FIG. 5) input from the input terminal 1 is converted into a 1-bit data input X shown in (b) in FIG. 5 by the ΔΣ modulator 2 shown in FIG. You. The 1-bit data input X is supplied to the instantaneous peak value level detector 3 and the delay line 6.

The instantaneous peak value detector 3 is constituted by a digital FIR filter having an audio band as a cutoff frequency, and detects the instantaneous peak value level A (FIG. 5 (c)) of the 1-bit data input X. The instantaneous peak value level A is an output that is digital data and has amplitude information.

When the instantaneous peak value level A is supplied, the gain generator 4 refers to the ROM table 4 and reads out the gain coefficient K corresponding to the predetermined instantaneous peak value level A. Output to the container 8.

The multiplier 8 is a digital multiplier, and outputs the multiplier output Z as Z = K * X (2) as shown in FIG.

The gain coefficient K at this time is given by K = f (X) / X (3) from the above equation (1) indicating the input / output conversion function.

Here, in the case of 1-bit data, the instantaneous peak value level of the low-frequency component signal is obtained as A by the instantaneous peak value level detector 3. From this, the gain generator 4
Generates a gain coefficient K as shown in FIG. 5D according to the level by K = f (A) / A (4). The equations (3) and (4) correspond to the transfer function of the converter 26 according to the equation (1).

FIG. 6 shows an example of the conversion characteristics stored in the ROM table 4. This is a transfer characteristic derived from equation (4) from the input / output conversion function of the nonlinear limiter shown in FIG. 3 and equation (1). here,
As shown in FIG. 5, the gain coefficient K when a sine wave is actually input is around 2.0 when the level A is around 0.0, and around 2.0 when the absolute value of the level A is around 1.0. , Around 1.0.

On the other hand, the 1-bit data input X is subjected to a delay operation for the delay time by the instantaneous peak value level detector 3 and the gain generator 4 by the delay line 6, and as shown in FIG. The output becomes a delay line output. After the timing is adjusted, the multiplier 8 in the gain controller 7 multiplies the gain coefficient (K). The multiplied output Z multiplied by K and obtained as shown in FIG.
The data is again converted into 1-bit data by the ΔΣ modulator 9 having the configuration shown in FIG. 5 and obtained as a 1-bit data output Y whose level is controlled as shown in FIG.

With respect to the 1-bit gain controller composed of the level controller 7 and the gain generator 4,
It is disclosed in Japanese Patent Application Laid-Open No. 8-274646 by the present applicant.

That is, the multiplication means multiplies the 1-bit data input to the multiplication means by, for example, a 16-bit multi-bit multiplication coefficient generated by the coefficient generation means. Then, the Δ 出力 modulation means performs ΔΣ modulation processing on the multiplied output of the multiplication means, and converts the multiplication output into 1-bit data.

In FIG. 1, the level controller 7
Is output to the analog FIR filter 10, and an audio signal component as shown in FIG. 5H is finally obtained from the output terminal 11.

The analog FIR filter 10 has, for example, a configuration as shown in FIG. As shown in FIG. 7, the analog FIR filter 10
D flip-flops D-FF1, D-FF2, D-FF
3, D-FF4 and D flip-flops D-FF1, D-FF
It comprises four resistors R1, R2, R3, R4 connected respectively to FF2, D-FF3, D-FF4. An analog FIR filter is formed by adding the currents from the four resistors R1, R2, R3, R4, and the output of the FIR filter is smoothed by a capacitor C and derived from an output terminal 33.

Input terminal 31 to which 1-bit data is supplied
Is connected to the data input terminal D of the D flip-flop D-FF1, and the output terminal Q of the D flip-flop D-FF1 is connected to the data input terminal D of the D flip-flop D-FF2. Output terminal Q to D
The flip-flop D-FF3 is connected to the data input terminal D, and the output terminal Q of the D flip-flop D-FF3 is connected to D
It is connected to the data input terminal D of the flip-flop D-FF4.

The clock input terminal 32 to which the clock CK is supplied is connected to each of the D flip-flops D-FF1, D-FF2, D
-FF3 and D-FF4, respectively.

Output terminal Q of D flip-flop D-FF1
To one end of a resistor R1 and a D flip-flop DF
One end of a resistor R2 is connected to the output terminal Q of F2, one end of the resistor R3 is connected to the output terminal Q of the D flip-flop D-FF3, and the resistor R4 is connected to the output terminal Q of the D flip-flop D-FF4. One end is connected.

The other ends of these resistors R1, R2, R3, R4 are connected to form an output terminal 33 from the connection point, and a capacitor C inserted between the connection point and ground.
Is used to smooth the analog output.

The analog signal from the analog FIR filter 10 is converted into an audible analog audio signal ((h) in FIG. 5) by passing through an analog LPF (not shown).

The audio signal component shown in FIG. 5 (h) has a gain of nearly 2.0 times at a low level with respect to the original audio signal shown in FIG. 5 (a). As the level increases, a limiter effect is gradually obtained.

As described above, according to the 1-bit data processing device, the 1-bit data is not converted into an analog signal once as in the prior art, but the 1-bit data is used as it is, and the gain operation according to the low-frequency component level is performed. To realize nonlinear limiter processing. That is, the level can be controlled with a simpler configuration than before and without deteriorating the sound quality.

The signal shown in (h) of FIG.
Was obtained when using the input / output function used in the nonlinear limiter shown in, but by using other characteristics,
Similar nonlinear processing is possible, and various effect effects can be realized.

Next, a second embodiment will be described. The second embodiment is also a 1-bit data processing device for controlling the level of 1-bit data obtained by subjecting an original analog audio signal to ΔΣ modulation processing. A level change process that changes over a long period of time, for example, an expand process is performed.

This 1-bit data processing device has a configuration as shown in FIG. The difference from the configuration shown in FIG. 1 is that an average energy level detector 35 is provided instead of the instantaneous peak value level detector 3, and that a new gain generator 38 and ROM 39 are used. is there.

The average energy level detector 35 detects the average energy level A of the low frequency component of the 1-bit data. The average energy level detector 35 has a digital FIR filter 36 and a square sum average calculator 37.

The average energy level A from the average energy level detector 35 is supplied to a gain generator 38.

The gain generator 38 reads a gain coefficient K corresponding to the average energy level A from a ROM table 39 storing input / output characteristics obtained by a function for performing the expanding process, and obtains the gain coefficient. K
Is supplied to the multiplier 8 of the level controller 7.

As a function for performing the above-described expand processing, for example, there are input / output characteristics, y = f (x) (1 ′) as shown in FIG. This is a characteristic in which the output level y increases nonlinearly as the input level x increases.

To realize such input / output characteristics, conventionally, a multi-bit PCM similar to that shown in FIG.
I had to use equipment.

In the case of the 1-bit data, the data itself has only two maximum and minimum amplitude values consisting of "0" and "1", and it is not possible to directly obtain a processing signal from a 1-bit data input by an input / output function. could not.

Therefore, in the 1-bit data processing device shown in FIG.
The average energy level of the low-frequency audio signal component is detected from the bit data input, and a gain generator 38 generates a conversion gain coefficient according to the average energy level. Then, based on this gain coefficient, the level controller 7 obtains 1-bit data whose level is controlled, in this case, 1-bit data output subjected to non-linear expanding processing.

The operation of the 1-bit data processing device will be described in detail with reference to the timing chart of FIG. First, the original analog audio signal ((a) in FIG. 10) input from the input terminal 1 is represented by ΔΣ shown in FIG.
The modulator 2 provides a 1-bit data input X shown in FIG. Here, the amplitude level of the original analog audio signal gradually increases in a longer time than in the instant. The 1-bit data input X is supplied to the average energy level detector 35 and the delay line 6.

The average energy level detector 3 comprises a digital FIR filter 36 having a cut-off frequency in the audio band and a square sum average calculator 37 for calculating the sum of squares of the filter output. The average energy level A shown in FIG. 10 (c) is detected. This average energy level A is digital data,
The output has amplitude information.

When the average energy level A is supplied, the gain generator 38 refers to the ROM table 39 and calculates a gain coefficient K corresponding to the predetermined average energy level A as shown in FIG. It is read out and output to the multiplier 8 of the level controller 7.

The multiplier 8 is a digital multiplier, and calculates and outputs the multiplier output Z as shown in the above equation (2).

The gain K at this time is expressed by the above equation (3) from the above equation (1 ′) indicating the input / output conversion function.

Here, in the case of 1-bit data, the average energy level is determined by the average energy level detector 3
5 gives A. From this, the gain generator 3
8 generates a gain coefficient K according to the level according to the above equation (4). The equations (3) and (4) correspond to the transfer function of the converter 26 according to the equation (1 ′).

FIG. 11 shows an example of the conversion characteristics stored in the ROM table 39. This is a transfer characteristic derived from equation (4) from the input / output conversion function shown in FIG. 9 and equation (1 ′).

Here, when an audio signal as shown in FIG. 10A is input, the gain coefficient K is 0.0 when the level A is around 0.0, and the gain A is 1.
When it is 0, it is 2.0, and the change is linear.

On the other hand, the 1-bit data input X is delayed by the delay time by the average energy level detector 35 and the gain generator 38 by the delay line 6 and the timing is adjusted. The gain coefficient is multiplied by K by the multiplier 8. The multiplied output Z shown in (e) of FIG. 10 obtained by multiplying by K is converted again into 1-bit data by the ΔΣ modulator 9 having the configuration shown in FIG. 2, and the level-controlled 1-bit data output Y ( This is obtained as (f) in FIG.

This 1-bit data output Y is converted into an analog signal by the alloglo FIR filter 10 having the configuration shown in FIG. 7 and passes through an analog LPF (not shown) to thereby produce an audible analog audio signal ((g) in FIG. 10). ). The amplitude level of the audio signal component shown in FIG. 10 (g) is gradually expanded in a longer time than the instant, similarly to the original audio signal shown in FIG. 10 (a).

As described above, according to the 1-bit data processing device, the 1-bit data is not returned to the analog signal once, but is used as it is as it is, and the gain operation according to the low-frequency component level is performed. And expand processing is realized. That is, the level can be controlled with a simpler configuration than before and without deteriorating the sound quality.

The signal shown in (g) of FIG. 10 is a case where the input / output function used in the expanding process is used. However, similar nonlinear processing is possible by using other characteristics. Various effect effects can be realized.

The 1-bit data processing device shown in FIG. 1 of the first embodiment and the second
In the 1-bit data processing device shown in FIG. 8 of the embodiment, the instantaneous peak value level detector 3 and the average energy level detector 35 of the low band signal component, the gain generator 4,
And the gain generator 38 are operated in synchronization with the sampling period unit used for the ΔΣ modulation process. However, by performing this synchronization at an integer multiple of the sampling period, the processing load can be reduced. Good.

FIG. 12 shows that the system clock of the instantaneous peak value level detector 3 and the gain generator 4 of the 1-bit data processing device of the first embodiment is 1/64 of the sampling frequency 64 fs used in the ΔΣ modulation processing. 2 shows a configuration in which the system clock fs is frequency-divided by the frequency divider 42.

The ΔΣ modulator 2 from the clock input terminal 41
Frequency 64fs used for ΔΣ modulation processing
Is supplied to the delay line 6 and the level controller 7 as a system clock. In addition, the instantaneous peak value level detector 3 and the gain generator 4 output 1/1 /
A system clock having a frequency fs divided by 64 is supplied.

As a result, a series of operation processing for gain control can be reduced to 1/64, and the scale of configuring hardware that executes in real time can be reduced.

Similarly, as shown in FIG. 13, the frequency divider 42 divides the system clock to the average energy level detector 35 and the gain generator 38 of the 1-bit data processing device according to the second embodiment. By using a clock having a frequency fs divided by 1/64, a series of operation processing for gain control can be reduced to 1/64, and the scale of configuring hardware that executes in real time can be reduced.

Further, the digital data processing method according to the present invention, that is, the level information of the amplitude of the low frequency component of the 1-bit data is detected, and the 1-bit data is generated based on the gain coefficient generated in accordance with the amplitude level information. If a digital data processing method characterized by controlling the level of the digital data is programmed as software and stored in a recording medium such as a ROM, for example, 1-bit data subjected to an effect processing in the amplitude direction can be easily obtained. Can be.

[0079]

According to the digital data processing apparatus of the present invention, the level of the 1-bit data can be easily changed according to the instantaneous peak value level of the amplitude of the low-frequency audio signal component of the 1-bit data, and Control can be performed without deteriorating sound quality.

Further, according to the digital data processing apparatus of the present invention, the level of the 1-bit data can be simply set according to the average energy level of the amplitude of the low-frequency audio signal component of the 1-bit data, and the sound quality can be improved. Can be controlled without impairment.

Further, according to the digital data processing method of the present invention, the level of the 1-bit data can be simplified and the sound quality can be reduced according to the level information of the amplitude of the low-frequency audio signal component of the 1-bit data. It can be controlled without loss.

[Brief description of the drawings]

FIG. 1 is a block diagram of a 1-bit data processing device according to a first embodiment of a digital data processing device and method according to the present invention.

FIG. 2 is a block diagram showing a detailed configuration of a ΔΣ modulator used in the 1-bit data processing device shown in FIG. 1;

FIG. 3 is a characteristic diagram showing input / output characteristics of a nonlinear limiter process.

FIG. 4 is a block diagram showing a configuration of a conventional multi-bit PCM device that executes the input / output characteristics shown in FIG.

FIG. 5 is a timing chart for explaining the operation of the 1-bit data processing device shown in FIG. 1;

FIG. 6 is a characteristic diagram showing an example of a conversion characteristic of a gain generator used in the one-bit data processing device shown in FIG. 1;

FIG. 7 is a circuit diagram showing a configuration of an analog FIR filter used in the one-bit data processing device shown in FIG. 1;

FIG. 8 is a block diagram showing a configuration of a 1-bit data processing device according to a second embodiment of the digital data processing device and method according to the present invention.

FIG. 9 is a characteristic diagram showing input / output characteristics of an expand process performed by the 1-bit data processing device shown in FIG. 8;

FIG. 10 is a timing chart for explaining the operation of the 1-bit data processing device shown in FIG. 8;

FIG. 11 is a characteristic diagram showing an example of a conversion characteristic of a gain generator used in the one-bit data processing device shown in FIG.

FIG. 12 shows a first embodiment shown in FIG.
It is a block diagram of a modification of a bit data processing device.

FIG. 13 shows a second embodiment shown in FIG.
It is a block diagram of a modification of a bit data processing device.

[Explanation of symbols]

2 ΔΣ modulator, 3 instantaneous peak level detector, 4 gain generator, 5 ROM table, 6 delay line, 7 level controller, 8 multiplier, 9 ΔΣ modulator

Claims (15)

[Claims] 1. A digital data processor for controlling the level of 1-bit data obtained by subjecting an audio signal to delta-sigma modulation processing, wherein an instantaneous peak value level of the amplitude of a low-frequency component of the 1-bit data is detected. An instantaneous peak value detecting means; a gain generating means for generating a gain coefficient according to the instantaneous peak value level detected by the instantaneous peak value detecting means; A digital data processing device comprising: level control means for controlling the level of 1-bit data. 2. The apparatus according to claim 1, further comprising delay means for delaying said one-bit data, wherein said level control means controls a level of said one-bit data delayed by said delay means. Digital data processing device. 3. The digital data according to claim 2, wherein said delay means delays said one-bit data by a time corresponding to a processing time of said instantaneous peak value detection means and said gain generation means. Processing equipment. 4. The apparatus according to claim 1, wherein said gain generation means generates said gain coefficient based on a storage means storing a value derived from a transfer function of a predetermined input / output characteristic. Digital data processing device. 5. The gain generating means according to claim 1, wherein said gain generating means generates said gain coefficient based on a storing means storing a value derived from a transfer function of a nonlinear input / output characteristic. Digital data processing device. 6. The digital data processing device according to claim 1, wherein operating frequencies of said instantaneous peak value level detecting means and said gain generating means are lower than a clock frequency used in said delta-sigma modulation processing. 7. A digital data processing device for controlling the level of 1-bit data obtained by subjecting an audio signal to delta-sigma modulation processing, wherein an average energy level for detecting an average energy level of a low-frequency component of the 1-bit data is provided. Detecting means; gain generating means for generating a gain coefficient according to the average energy level detected by the average energy level detecting means; and a level of the 1-bit data based on the gain coefficient generated by the gain generating means. A digital data processing device comprising: level control means for controlling. 8. The apparatus according to claim 7, further comprising delay means for delaying said one-bit data, wherein said level control means controls a level of said one-bit data delayed by said delay means. Digital data processing device. 9. The digital data processing device according to claim 8, wherein said delay means delays said 1-bit data by a time corresponding to a processing time of said average energy level detection means and said gain generation means. apparatus. 10. The gain coefficient generating means according to claim 7, wherein said gain generating means generates said gain coefficient based on a storing means storing a value derived from a transfer function of a predetermined input / output characteristic. Digital data processing device. 11. The gain coefficient generating means according to claim 7, wherein said gain generating means generates said gain coefficient based on a storage means storing a value derived from a transfer function of a non-linear input / output characteristic. Digital data processing device. 12. The digital data processing apparatus according to claim 7, wherein operating frequencies of said average energy level detecting means and said gain generating means are lower than a clock frequency used in said delta sigma modulation processing. 13. A digital data processing method for controlling the level of 1-bit data obtained by subjecting an audio signal to delta-sigma modulation processing, comprising: detecting level information of the amplitude of a low-frequency component of the 1-bit data; A digital data processing method, wherein the level of the 1-bit data is controlled based on a gain coefficient generated according to the amplitude level information. 14. The digital data processing method according to claim 13, wherein said amplitude level information is an instantaneous peak value level of the amplitude of a low-frequency component of said 1-bit data. 15. The digital data processing method according to claim 13, wherein said amplitude level information is an average energy level of a low-frequency component of said 1-bit data.