JPH11510319A - パターン内に間隔層を製造する方法 - Google Patents
パターン内に間隔層を製造する方法Info
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- JPH11510319A JPH11510319A JP9508004A JP50800497A JPH11510319A JP H11510319 A JPH11510319 A JP H11510319A JP 9508004 A JP9508004 A JP 9508004A JP 50800497 A JP50800497 A JP 50800497A JP H11510319 A JPH11510319 A JP H11510319A
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- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
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- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
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- H—ELECTRICITY
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- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
- H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
- H10P14/6326—Deposition processes
- H10P14/6328—Deposition from the gas or vapour phase
- H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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Abstract
(57)【要約】
間隔層をパターン内に形成する方法において第１の工程でパターンを異方性乾式エッチングにより形成し、もう１つの工程で圧力ｐ＝０．２〜１バール及び温度２００℃〜４００℃で酸化物層を有機性前駆物質で析出する。
Description
【発明の詳細な説明】
パターン内に間隔層を製造する方法
本発明はパターン内に間隔層を製造する方法に関する。
半導体技術分野では間隔層、いわゆるスペーサは重要な意義を有する。
スペーサは例えばパターン（例えば孔又はトレンチ）内に孔、通路又はトレン
チの横方向の電気的絶縁、いわゆる芽晶層の析出又は拡散バリヤの形成のために
製造される。
絶縁スペーサを形成するための材料としては典型的には二酸化シリコン（Ｓｉ
Ｏ2）が使用される。
図１に基づきＳｉＯ2スペーサを形成するための従来法について以下に記載す
る。
図１にはスペーサを形成する材料を析出する前のパターン１００（この場合例
えばトレンチであってもよい）が示されている。このパターン１００は図ａに示
されている例では第１の層１０２及び第２の層１０４から成る多層構造物中に形
成されている。
第１の層１０２は典型的にはトランジスタ（フロントエンド）を有するシリコ
ン基板であり、第２の層１０４はトランジスタ（バックエンド）の配線部（金属
化部）の役目をし、その際第２の層はＳｉＯ2から成り、そこに金属製軌道が埋
め込まれている。
パターン１００の形成後ＳｉＯ2を析出し、図１ｂに示されているようにＳｉ
Ｏ2層１０６を層１０４の表面、パターン１００の側壁並びにパターン１００の
底部に形成する。
スペーサを完成するために、図１ｃに見られるようにパターン１００の底部１
０８を露出する異方性プラズマエッチングを行う。
同時にこのプラズマエッチングにより層１０４の上方のＳｉＯ2層１０６及び
層１０４の若干分を除去する。それというのも同様に図１ｃに見られるようにウ
ェハの表面上のエッチング率がパターンの底部よりも高くなるからである。
従来技術から公知の方法についての上の記載から、この公知方法がパターン内
にスペーサを作るのにパターン形成工程、スペーサを形成する材料の析出工程、
及びパターン底部をエッチングプロセスにより露出させる工程から成る出費の多
い処理工程を含んでおり、その際今日益々深くなっていくパターンではウェハ表
面とパターンの底部に対する異なるエッチング率が益々難問を提示する。
更に上記の従来技術に基づくこれまでの方法はパターン１００の底部１０８か
らＳｉＯ2層を除去するだけのものには適しておらず、この方法では一般に水平
領域のＳｉＯ2層も除去される。
上記の従来技術から出発して本発明の課題は、パターン内に間隔層を形成する
ための簡略化された方法を提供することにある。
この課題は請求項１に記載の方法により解決される。
本発明は以下の工程、
パターンを形成するためのパターン化すべき層の異方性乾式エッチング、
エッチング残渣の除去によるパターンの浄化、
圧力ｐ＝０．２〜１バール及び温度２００℃〜４００℃で有機性シリコン前駆
物質及びオゾンでの二酸化シリコンの析出
によりパターン内に間隔層を形成する方法を提供する。
本発明は、パターンを形成するための異方性乾式エッチングがとりわけパター
ンの底部に損傷、変態及び／又は汚染又は注入を生じることになるという認識に
基づく。エッチング残渣を除去して全表面を浄化するための、典型的には１〜３
％のフツ化水素酸（ＨＦ）によるその後の湿式エッチング工程の継続時間は、パ
ターンの側壁は浄化するが、しかしパターン底部の変態は完全には除去ししない
ような短時間になるように選択されなければならない。引続いてのスペーサを形
成する層の同形析出中の適した処理方法は、パターンの底部には析出は起こさず
、従ってこの析出プロセスにより所望の横方向のスペーサだけが形成されるよう
に続けられる。従って上記の公知方法の終わりに必要とされている付加的エッチ
ング工程は省略される。
本発明の有利な実施態様によれば湿式化学による浄化は典型的には１〜３％の
フツ化水素酸（ＨＦ）により行われる。
本発明の他の有利な実施態様によればシリコン前駆物質の析出はＯ3−ＴＥＯ
Ｓ−ＣＶＤプロセスにより行われる。
本発明のその他の有利な実施態様は従属請求項に明示されている。
添付の図面に基づき本発明の有利な実施例を以下に詳述する。その際
図１は従来技術に基づく方法でスペーサを形成するために必要な工程を示し、
図２は本発明方法によるスペーサを形成するために必要な工程を示す。
本発明方法を図２に基づき以下に詳述する。
第１の工程でパターン２０２を形成するためパターン化すべき層２００の異方
性乾式エッチングが行われる。
この第１の工程の後図２ａに示されているようにパターンが形成される。
図２ａに示されている例えばトレンチ又は孔の形のパターン２０２は側壁２０
４及び底部２０６を含んでいる。
層２００は例えば基板又はウェハである。
パターン化すべき層２００は既に図１について記載したように単一の層から形
成される必要はなく、これが多重層から形成されていてもよいことを付け加えて
おく。
更に既に仕上げ処理されたウェハを使用することもできる。
パターン化すべき層２００の形式の選択は所定の用途に直接左右され、異なる
半導体製造技術により異なる。
ここに記載する実施例では異方性乾式エッチングは異方性プラズマエッチング
により行われる。
その側壁２０４にスペーサが形成されるパターン２０２を形成する異方性プラ
ズマエッチング法により、とりわけパターン２０２の底部２０６にプラズマエッ
チングプロセスの異方性により損傷、変態及び／又は汚染又は注入を生じる。こ
の結果既にパターン形成中にパターン２０２の底部２０６は側壁２０４と異なっ
て前処理されていることが分かる。
この異なる前処理は本発明方法の第１の重要な特徴である。この異なる前処理
を他の異方性乾式エッチングプロセスにより行うこともできることに言及してお
く。
生じる汚染及びエッチング残渣はエッチングプロセス後に除去しなけれならな
い。これは例えば湿式化学による浄化工程又は等方性プラズマ浄化工程により行
うことができる。
次の工程でパターン化すべき層２００上並びにパターン２０２の範囲に有機性
のシリコン前駆物質及びオゾンで二酸化シリコン（ＳｉＯ2）を圧力ｐ＝０．２
〜１バール及び温度２００℃〜４００℃で析出させる。有機性シリコン前駆物質
は当業者の間でそれ自体公知であり、シリコン前駆体を形成する材料を意味する
。
上記のプロセスパラメータによる有機性シリコン前駆物質のこの析出はスペー
サを同形析出するのに適した処理工程である。
パターン２０２の形成中の上記の図２ａに基づくプロセス工程によりパターン
２０２の底部２０６に析出が行われないような同形析出が生じる。従ってこの析
出により図２ｂに見られるようにスペーサ２０８のみが形成される。
このスペーサにより例えば横方向の電気的絶縁は実現される。
有利な実施例によればＳｉＯ2析出はいわゆるＴＥＯＳプロセスによりシリコ
ン前駆物質としてのＴＥＯＳ（ＴＥＯＳ＝テトラエチルオルトシリケート）で行
われる。
また本発明の更に有利な実施例によれば上記のＴＥＯＳプロセスはＯ3−ＴＥ
ＯＳ−ＣＶＤプロセスにより行われる。このプロセスに必要なプロセスパラメー
タは以下の通りである。
ウェハガスシャワー−間隔＝５〜２５ｓｃｃｍ
（Ｏ3−ＴＥＯＳ−ＣＶＤプロセスを実施する装置は当業者の間でそれ自体公
知であり、従って上記のウェハとガスシャワーとの間隔については詳細に説明す
る必要はないものと考える。）
（酸素＋オゾン）流＝１０００〜１００００ｓｃｃｍ
（ＴＥＯＳ＋ヘリウム）流＝１００〜３０００ｓｃｃｍ
酸素オゾン混合物中のオゾンの分量＝５〜２０重量％
Ｏ3−ＴＥＯＳ−ＣＶＤプロセスはいわゆるＳＡＣＶＤプロセス（ＳＡＣＶＤ
＝Ｓｕｂａｔｏｍｏｓｆｅｒｉｃ Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓ
ｉｔｉｏｎ＝準大気圧による化学蒸着）である。
上記のトレンチ又は孔の他に他のパターンを使用し、このパターンの底部範囲
は空けておき、それに対して側壁にはスペーサ又は酸化スペーサを形成すること
もできることを指摘しておく。
Claims (1)
- 【特許請求の範囲】 １． パターン（２０２）を形成するためにパターン化すべき層（２００）を異 方性乾式エッチングし、 エッチング残渣を除去してパターン（２０２）を浄化し、 圧力ｐ＝０．２〜１バール及び温度２００℃〜４００℃で有機性シリコン前駆 物質とオゾンで二酸化シリコンを析出する ことを特徴とするパターン内に間隔層を形成する方法。 ２． パターン化すべき層（２００）がウェハであることを特徴とする請求項１ 記載の方法。 ３． 浄化工程の際にパターンの側壁のエッチング残渣を除去し、パターン（２ ０２）の底部の変態は除去しないことを特徴とする請求項１又は２記載の方法。 ４． 形成すべき層（２００）がトレンチ又は孔であることを特徴とする請求項 １乃至３の１つに記載の方法。 ５． 析出工程が有機性前駆物質による析出プロセスを含んでいることを特徴と する請求項１乃至４の１つに記載の方法。 ６．析出プロセスをＯ3−ＴＥＯＳ−ＣＶＤプロセスにより実施し、その際Ｏ3− ＴＥＯＳ−ＣＶＤプロセスが以下のプロセスパラメータ、即ち ウェハとガスシャワー−間隔＝５〜２５ｍｍ （酸素＋オゾン）流＝１０００〜１００００ｓｃｃｍ （ＴＥＯＳ＋ヘリウム）流＝１００〜３０００ｓｃｃｍ 酸素オゾン混合物中のオゾンの分量＝５〜２０重量％ を有していることを特徴とする請求項５記載の方法。
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19528746.0 | 1995-08-04 | ||
| DE19528746A DE19528746C1 (de) | 1995-08-04 | 1995-08-04 | Verfahren zum Erzeugen einer Siliziumdioxidschicht auf Oberflächenabschnitten einer Struktur |
| PCT/DE1996/001277 WO1997006556A1 (de) | 1995-08-04 | 1996-07-12 | Verfahren zum erzeugen einer abstandsschicht in einer struktur |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11510319A true JPH11510319A (ja) | 1999-09-07 |
| JP3590636B2 JP3590636B2 (ja) | 2004-11-17 |
Family
ID=7768730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50800497A Expired - Lifetime JP3590636B2 (ja) | 1995-08-04 | 1996-07-12 | パターン内に間隔層を製造する方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6030900A (ja) |
| EP (1) | EP0842532B1 (ja) |
| JP (1) | JP3590636B2 (ja) |
| KR (1) | KR100403443B1 (ja) |
| DE (1) | DE19528746C1 (ja) |
| SG (1) | SG54352A1 (ja) |
| TW (1) | TW299468B (ja) |
| WO (1) | WO1997006556A1 (ja) |
Families Citing this family (295)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0959496B1 (en) | 1998-05-22 | 2006-07-19 | Applied Materials, Inc. | Methods for forming self-planarized dielectric layer for shallow trench isolation |
| DE19935130C1 (de) * | 1999-07-27 | 2001-02-22 | Siemens Ag | Verfahren zur Herstellung eines Kontaktloches für ein Halbleiterspeicherbauelement |
| DE10055290C1 (de) | 2000-11-08 | 2002-07-25 | Infineon Technologies Ag | Herstellungsverfahren für eine integrierte Schaltung |
| DE10217386A1 (de) * | 2002-04-18 | 2003-11-13 | Infineon Technologies Ag | Verfahren zum Herstellen eines elektrisch leitenden Kontaktes auf einem Substrat |
| TW200422424A (en) * | 2002-08-18 | 2004-11-01 | Asml Us Inc | Low temperature deposition of silicon oxides and oxynitrides |
| TW200408015A (en) * | 2002-08-18 | 2004-05-16 | Asml Us Inc | Atomic layer deposition of high K metal silicates |
| TW200408323A (en) * | 2002-08-18 | 2004-05-16 | Asml Us Inc | Atomic layer deposition of high k metal oxides |
| US20050070126A1 (en) * | 2003-04-21 | 2005-03-31 | Yoshihide Senzaki | System and method for forming multi-component dielectric films |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4476622A (en) * | 1981-12-24 | 1984-10-16 | Gte Laboratories Inc. | Recessed gate static induction transistor fabrication |
| US5223736A (en) * | 1989-09-27 | 1993-06-29 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
| JP3123061B2 (ja) * | 1990-06-13 | 2001-01-09 | ソニー株式会社 | バイアスｅｃｒ―ｃｖｄ法による埋め込み平坦化方法 |
| US5069747A (en) * | 1990-12-21 | 1991-12-03 | Micron Technology, Inc. | Creation and removal of temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on exposed, permanent silicon dioxide structures |
| EP0597603A3 (en) * | 1992-11-13 | 1998-03-11 | Digital Equipment Corporation | Trench isolation planarization using a hard mask |
| EP0631305B1 (de) * | 1993-06-23 | 1998-04-15 | Siemens Aktiengesellschaft | Verfahren zur Herstellung eines Isolationsgrabens in einem Substrat für Smart-Power-Technologien |
| US5489553A (en) * | 1995-05-25 | 1996-02-06 | Industrial Technology Research Institute | HF vapor surface treatment for the 03 teos gap filling deposition |
| US6009827A (en) * | 1995-12-06 | 2000-01-04 | Applied Materials, Inc. | Apparatus for creating strong interface between in-situ SACVD and PECVD silicon oxide films |
| US5849635A (en) * | 1996-07-11 | 1998-12-15 | Micron Technology, Inc. | Semiconductor processing method of forming an insulating dielectric layer and a contact opening therein |
-
1995
- 1995-08-04 DE DE19528746A patent/DE19528746C1/de not_active Expired - Lifetime
-
1996
- 1996-07-12 JP JP50800497A patent/JP3590636B2/ja not_active Expired - Lifetime
- 1996-07-12 EP EP96923843A patent/EP0842532B1/de not_active Expired - Lifetime
- 1996-07-12 WO PCT/DE1996/001277 patent/WO1997006556A1/de not_active Ceased
- 1996-07-12 KR KR10-1998-0700829A patent/KR100403443B1/ko not_active Expired - Lifetime
- 1996-07-12 US US09/011,375 patent/US6030900A/en not_active Expired - Lifetime
- 1996-07-17 TW TW085108678A patent/TW299468B/zh not_active IP Right Cessation
- 1996-07-22 SG SG1996010294A patent/SG54352A1/en unknown
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|---|---|
| SG54352A1 (en) | 1998-11-16 |
| KR19990036161A (ko) | 1999-05-25 |
| EP0842532A1 (de) | 1998-05-20 |
| US6030900A (en) | 2000-02-29 |
| KR100403443B1 (ko) | 2003-12-18 |
| TW299468B (ja) | 1997-03-01 |
| EP0842532B1 (de) | 2002-10-02 |
| WO1997006556A1 (de) | 1997-02-20 |
| JP3590636B2 (ja) | 2004-11-17 |
| DE19528746C1 (de) | 1996-10-31 |
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