JPH1166844A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] During a refresh operation, the peak current of the S / A operation increases, and the power supply circuit corresponding to a normal access lacks current supply capability and the level of each power supply voltage drops. As a result, the refresh operation cannot be performed reliably due to a shift in operation timing, and in order to avoid this, a plurality of power generation circuits are provided to increase the occupied area and the power consumption. SOLUTION: This semiconductor memory device involves refreshing a memory cell, and delays predetermined signals lez and prepz only at the time of the refresh so that a refresh operation is performed in accordance with a delay of an operation timing due to a voltage drop at the time of the refresh. It is configured to be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a volatile semiconductor memory device with a refresh operation. DRAM (Dynamic Random Access Memo)
ry) and volatile memories such as synchronous DRAM (SDRAM) require a refresh operation. This refresh operation is a rewrite operation of a memory cell, and a refresh time is determined by a rule, and supply currents of various power supply generation circuits are set according to the number of S / As operating at one time. ing.

In recent years, semiconductor memory devices have been introduced which attempt to reduce the current consumption by subdividing the activation array and speed up the access operation. Also in these chips (semiconductor storage devices), the number of S / As at the time of refresh is the same as that of the conventional chip, so that a large difference occurs in the current consumption of each power generation circuit between active and refresh. ing. Therefore, a device provided with a plurality of power generation circuits has been proposed, but has problems in terms of the occupied area of the power supply unit and power consumption. There is a demand for a semiconductor memory device capable of performing a refresh operation.

[0003]

2. Description of the Related Art FIG. 1 is a block diagram conceptually showing a memory cell array section and a power supply generating circuit in an example of a conventional semiconductor memory device. In FIG. 1, reference numeral 101 indicates
Denotes a semiconductor memory device (memory chip), 121 to 124 denote memory cell array units, 103 denotes a power supply voltage generator, and 104 denotes a boost level generator.

In the conventional semiconductor memory device (for example, SDRAM) shown in FIG. 1, a common power supply voltage generator 103 and a boosted level generator 104 have a power supply for a plurality (for example, four) of memory cell array units 121 to 124. It is configured to supply a voltage. Here, the power supply voltage generator 103 includes, for example, each of the memory cell array units 121 to 121.
A power supply voltage is supplied to an S / A (sense amplifier) 124, and a boosted level generator 104 generates a boosted level used to drive a selected word line in each of the memory cell array units 121 to 124. .

In a conventional DRAM (SDRAM),
The refresh time is, for example, 8k times / 64 according to regulations.
msec., and in a 256 Mbit DRAM, the refresh operation is performed 8k times in 64 milliseconds. That is, S that operates at once
/ A (sense amplifier) number is 256M は 8k times = 32
The number becomes k, and the S / A that is four times as many as 8 k in the normal access (at the time of reading or writing) operates simultaneously.

As a result, the peak current of the S / A operation increases, and as a result, the semiconductor memory provided with the power supply voltage generator 103 having a driving capability corresponding to a normal access (in a normal operation mode). In the device, S in a refresh operation (in a refresh operation mode)
The time required for the S / A to amplify the potential difference between the pair of bit lines is longer than that during normal access due to insufficient current supply capability for / A. Conventionally, a word line in one memory cell array section is selected during normal access, whereas a word line in four memory cell array sections is selected during a refresh operation, for example. ing. Therefore, the boosted level generator 104 for driving the word line must drive different loads during normal access (during normal operation mode) and during refresh operation (during refresh operation mode). .

Here, for example, a refresh operation of a DRAM is a rewrite operation of a memory cell, a sense amplifier (S / A) operates after a word line (WL) rises, and a bit line (BL, The refresh operation is performed by closing the word line when the level difference of (/ BL) becomes sufficient and repeating these operations. In this series of operations, when the voltage drop (bump down) of the power supply occurs, the problem is that the rising of the word line is delayed and the sensing operation starts before data from the memory cell comes out. And that the word line is closed when the bit line is not fully opened.

FIG. 2 is a block diagram conceptually showing a memory cell array portion and a power supply generating circuit in another example of the conventional semiconductor memory device. In FIG.
Denotes a semiconductor memory device (memory chip), 121 to 124 denote memory cell array units, 131 to 134 denote power supply voltage generators, and 141 to 144 denote boosted level generators.

In the above-described conventional semiconductor memory device shown in FIG. 1, a plurality of memory cell array units 121 to 124 are provided.
, A common power supply unit (power supply voltage generator 103 and boosted level generator 104) is provided. On the other hand, the conventional semiconductor memory device shown in FIG. In order to cope with an increase in current consumption of A (sense amplifier), each memory cell array unit 121
To the power supply voltage generators 131-1 to 131-124, respectively.
34 and booster level generators 141 to 144 are provided to correspond to the current consumption during the refresh operation. Here, the plurality of power supply voltage generators 131 to 134 and the boosted level generators 141 to 144 may be configured to be activated only during the refresh operation.

FIG. 3 is a block circuit diagram showing a main part of an example of a conventional semiconductor memory device. FIG. 4 is a timing chart for explaining a refresh operation of the semiconductor memory device of FIG. 5 is a block circuit diagram showing a configuration example of a main part of a memory cell array unit in a conventional semiconductor memory device. 3 and 5, reference numeral 105 is a precharge control circuit, 106 is a row control circuit (row control circuit), 107 is a word decoder control circuit, and 110 is a sense amplifier control circuit (S
/ A control circuit). In FIG. 5, reference numeral 108 denotes a word decoder, 109 denotes a column decoder, 111 denotes a sense amplifier activating circuit (S / A activating circuit), and 112 denotes a sense amplifier (S / A).

As shown in FIG. 3 and FIG.
The system control circuit 106 supplies a row address strobe signal /
The row system control circuit 106 outputs a signal brasz to the word decoder control circuit 107 and outputs a signal prez to the precharge control circuit 105. Word decoder control circuit 107
Are a plurality of word decoders (word decoder arrays) 10
8. The signal pwlz is output to the S / A control circuit 110 and the precharge control circuit 105, and the precharge control circuit 105 feeds back the signal prepz to the row control circuit 106. Then, the S / A control circuit 110 outputs a signal lez to a plurality of S / A (sense amplifier arrays) 112.

As shown in FIG. 3, a precharge control circuit 105 includes a NAND gate NAND5 to which signals prez and pwlz are input, and a plurality of inverters I51 to I51.
I55, a plurality of resistors R51 to R54, and a plurality of capacitors C51 to C54. The S / A control circuit 110 includes a plurality of inverters I11
To I18, a plurality of resistors R11 to R15, a plurality of capacitors C11 to C15, and a NOR gate NOR1.

As shown in FIG. 5, a plurality of word decoders (word decoder columns) 108 receive a signal pwlz from a word decoder control circuit 107, receive a row address, and select a predetermined word line WL. It has become. Also, the S / A activation circuit 111
Receives the signal lez from the S / A control circuit 110 and supplies the signals nsa and psa to a plurality of S / A (sense amplifier arrays) 112.

The column decoder 109 receives a column address and selects a corresponding S / A 112. Each S / A
112 is a signal nsa from the S / A activation circuit 111,
psa, and receives the corresponding bit line BL,
It amplifies the minute potential from the memory cell MC provided at the intersection of / BL and the word line WL selected by the word decoder 108.

Next, a refresh operation of the conventional semiconductor memory device will be described. As shown in FIG. 4, in the refresh operation of the semiconductor memory device of FIG. 3, first, when row address strobe signal / ras changes from high level "H" to low level "L", row control is performed. Circuit 106
(The row access signal) and the signal prez rise from the low level “L” to the high level “H”.

Further, an output signal pwlz (a signal from which the word line WL is raised) of the word decoder control circuit 107 is generated (from low level "L" to high level "H").
), And the signal lez that activates the sense amplifier operation output from the S / A control circuit 110 is connected to the resistor R11,
R13 to R15 and capacitors C11 and C13 to C1
After rising by a predetermined time (delay time DT12) such as 5 or the like, the signal rises from the low level "L" to the high level "H". Also, the output signal prepz of the precharge control circuit 105
Indicates that the signal prel is high when the signal pwlz is at a high level "H".
When z changes to a high level “H”, the resistance R51
To R54 and a predetermined time (delay time DT11) by the capacitors C51 to C54, etc.
Rises to a high level "H". That is, the precharge control circuit 105 outputs the signal pre at a predetermined timing.
The signal pz is generated and returned to the row control circuit 106 to execute a precharge operation.

That is, the row control circuit 106 receives the signal prez, changes the output signal brasz from the high level “H” to the low level “L”, and accordingly outputs the output signal pwlz of the word decoder control circuit 107.
Also changes from the high level “H” to the low level “L”. Further, in response to a change in the signal pwlz, the S / A control circuit 11
The signal lez output from 0 changes from a high level "H" to a low level "L" after being delayed by a predetermined time by the resistors R11 and R12 and the capacitors C11 and C12.

Here, the delay time DT12 in the S / A control circuit 110 and the delay time DT11 in the precharge control circuit 105 are determined by the resistance of the resistor and the capacitor.
It is predetermined by the delay. FIG. 6 is a circuit diagram showing an example of the S / A activation circuit in the memory cell array section of FIG. 5, and FIG. 7 is a circuit diagram showing an example of a word decoder in the memory cell array section of FIG. The S / A activation circuit, S / A and word decoder have a common configuration in the conventional semiconductor memory device and the semiconductor memory device to which the present invention is applied.

As shown in FIG. 6, S / A activating circuit 111 (11) includes inverter I3, P-channel MOS transistor QP3 receiving at its source a power supply voltage (VDD) supplied from a power supply voltage generator. And N-channel MOS transistors QN31 to QN33. The S / A 112 (12) includes P-channel MOS transistors QP41 and QP42 and N-channel MOS transistors QN41 and QN42.

In the S / A activation circuit 111, when the output signal lez from the S / A control circuit 110 is at a low level "L", the transistors QP3 and QN33 are switched off and the transistors QN31 and QN32 are switched on. The signals psa and nsa become VDD / 2 and S
/ A112 to a reset state (precharge state),
When the signal lez is at the high level "H", the transistors QP3 and QN33 are switched on and the transistors QN31 and QN32 are switched off, the signal psa becomes VDD and the signal nsa becomes VSS (GND), and S
/ A112 is set to an operating state (activated state).

As shown in FIG. 7, the word decoder 1
08 (8) is a NAND gate NAND8, an inverter I
8. P-channel MOS transistors QP81 to QP81 receiving at their sources the boosted level (VPP) from the boosted level generator
QP83 and N-channel MOS transistor QN8
1 to QN83. When both the signal pwlz and the address signal from the word decoder control circuit 107 input to the NAND gate NAND8 are at the high level "H", the word decoder 108 selects the corresponding word line WL (high level "H"). ing.

[0022]

As described above, FIG.
In the conventional semiconductor memory device shown in (1), a common power supply unit (power supply voltage generator 103 and boost level generator 104) is provided for a plurality of memory cell array units 121 to 124 during normal access (read or write). , The current supply capability of the power supply unit (the power supply voltage generator 103 and the boost level generator 104) is insufficient due to the increase in the current consumption during the refresh operation. As a result, each power supply voltage drops below a predetermined level, the operation timing is shifted, and a normal refresh operation cannot be performed.

That is, as described with reference to FIG. 6, delay time DT12 in S / A control circuit 110 and delay time DT in precharge control circuit 105
Numeral 11 is predetermined by a CR delay of a resistor and a capacitor. In a semiconductor memory device having a power supply circuit suitable for a current consumption required for normal access, each power supply is insufficient due to a shortage of current supply capability during a refresh operation. Since the voltage dropped below a predetermined level, timing could not be taken well.

In the conventional semiconductor memory device shown in FIG. 2, each of the memory cell array sections 121 to 121 is adapted to cope with an increase in the current consumption of the sense amplifier during the refresh operation.
124, power supply voltage generators 131 to 13 respectively.
4 and booster level generators 141 to 144 are provided.
When the power supply units 1 to 134 and the boost level generators 141 to 144 are provided, not only does the area occupied by the power supply unit increase, which hinders integration, but also increases power consumption.

In view of the above-mentioned problems of the conventional semiconductor memory device, the present invention provides a reliable refresh operation without increasing the area occupied by the power supply unit and power consumption by providing a plurality of power supply generation circuits. The purpose of the present invention is to provide a semiconductor memory device capable of performing the following.

[0026]

According to the present invention, there is provided a semiconductor memory device which involves refreshing a memory cell, wherein a predetermined signal is delayed only at the time of refreshing to thereby reduce an operation timing due to a voltage drop at the time of refreshing. A semiconductor memory device characterized in that the refresh operation is performed in accordance with the delay of

According to the semiconductor memory device of the present invention, the predetermined signal is delayed only at the time of refresh, and the refresh operation is performed in accordance with the delay of the operation timing due to the voltage drop at the time of refresh. As a result, a reliable refresh operation can be performed without increasing the occupied area of the power supply unit and increasing power consumption due to the provision of a plurality of power generation circuits as in a conventional semiconductor memory device.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor memory device according to the present invention will be described with reference to the drawings. FIG. 8 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in an example of a semiconductor memory device to which the present invention is applied. 8, reference numeral 1 denotes a semiconductor memory device (memory chip), 21 to 24 denote memory cell array units, 3 denotes a power supply voltage generator, and 4 denotes a boost level generator.

The semiconductor memory device (for example, SDRAM) of the present embodiment shown in FIG. 8 uses a common power supply voltage generator 3 and a boosted level generator 4 similarly to the conventional semiconductor memory device shown in FIG. Each power supply voltage is supplied to a plurality (for example, four) of the memory cell array units 21 to 24. FIG. 9 is a block circuit diagram showing a main part configuration in one embodiment of the semiconductor memory device according to the present invention. FIG. 10 is a timing chart for explaining a refresh operation of the semiconductor memory device in FIG. FIG.
FIG. 2 is a block circuit diagram showing a configuration example of a main part of a memory cell array in a semiconductor memory device to which the present invention is applied.

9 and 11, reference numeral 5 is a precharge control circuit, 6 is a row control circuit (row control circuit), 7 is a word decoder control circuit, and 1
0 indicates a sense amplifier control circuit (S / A control circuit). In FIG. 11, reference numeral 8 denotes a word decoder, 9 denotes a column decoder, 11 denotes a sense amplifier activating circuit (S / A activating circuit), and 12 denotes a sense amplifier (S / A).

As shown in FIGS. 9 and 11, ro
The w-system control circuit 6 has a row address strobe signal / r
As is supplied, the row control circuit 6 outputs a signal brasz to the word decoder control circuit 7 and outputs a signal prez to the precharge control circuit 5. The word decoder control circuit 7 outputs a signal pwlz to the plurality of word decoders 8, the S / A control circuit 10 and the precharge control circuit 5, and the precharge control circuit 5 transmits a signal pwlz to the row control circuit 6. Signal pr
Return epz. Then, the S / A control circuit 10 outputs a signal lez to the plurality of S / As 12.

Here, in the semiconductor memory device of this embodiment, the precharge control circuit 5 and the S / A control circuit 1
A control signal refz is supplied for 0. The control signal refz is generated by the control signal generation circuit (13), and the configuration of the control signal generation circuit will be described later in detail. As shown in FIG. 9, the precharge control circuit 5 includes a NAND gate NAND5 to which signals prez and pwlz are input, and a plurality of inverters I5
1 to I58, a plurality of resistors R51 to R56, a plurality of capacitors C51 to C56, and a transfer gate TG
51 and TG52. Here, FIG.
As is clear from the comparison with the conventional precharge control circuit 105 shown in FIG. 5, in the precharge control circuit 5 of this embodiment, the inverters I56 and I57 and the resistors R55 and R55
A delay circuit 50 composed of a capacitor 56 and capacitors C55 and C56 is added, and the connection of the delay circuit 50 is controlled by a control signal refz.

At the time of normal access (during read and write operations), the control signal refz becomes low level "L", and the transfer gate TG51 is switched off and T
G52 is switched on, and the output signal pr of the precharge control circuit 5 of the present embodiment is obtained by a circuit configuration similar to that of the conventional precharge control circuit 105 without involving the delay circuit 50.
The delay time DT11 is given to epz. On the other hand, at the time of refresh operation, the control signal refz becomes high level "H", the transfer gate TG51 is switched on, the TG 52 is switched off, the delay circuit 50 is inserted in series, the delay time becomes long, and the precharge control circuit 5 is given a delay time DT1.

That is, in the present embodiment, a common power supply unit (power supply voltage generator 3 and boosted level generator 4) is provided for the plurality of memory cell array units 21 to 24. At the time of access, the output signal prepz of the precharge control circuit 5 has a delay time DT1
Give one. At the time of the refresh operation, each power supply voltage drops below a predetermined level due to the shortage of current supply capability of the power supply unit (the power supply voltage generator 3 and the boost level generator 4), and the operation speed (change in signal level) decreases. But
In order to cope with this delay, the output signal prepz of the precharge control circuit 5 is provided with a delay time DT during normal access.
A delay time DT1 greater than 11 is given to match (delay) the operation timing.

As shown in FIG. 9, the S / A control circuit 10 includes a plurality of inverters I11 to I21, a plurality of resistors R11 to R17, and a plurality of capacitors C11 to C1.
7, NOR gate NOR1, and transfer gates TG11, TG12. here,
As is apparent from a comparison with the conventional S / A control circuit 110 shown in FIG. 3, the S / A control circuit 10 of the present embodiment includes inverters I19 and I20, resistors R16 and R17, and capacitors C16 and C17. Delay circuit 1
00 and the connection of the delay circuit 100 is controlled by the control signal r.
efz.

At the time of normal access (during normal operation mode: read and write operations), the control signal refz
Becomes low level "L" and the transfer gate TG11
Is switched off, the TG 12 is switched on, and the output signal lez of the S / A control circuit 10 of the present embodiment is delayed by a circuit configuration similar to that of the conventional S / A control circuit 110 without involving the delay circuit 100. A time DT12 is given. On the other hand, during refresh operation (in refresh operation mode)
, The control signal refz becomes high level “H”, the transfer gate TG11 is switched on, the TG12 is switched off, the delay circuit 100 is inserted in series, the delay time becomes longer, and the S / A control circuit 10 Output signal lez
Is provided with a delay time DT2.

That is, in the present embodiment, a common power supply unit (power supply voltage generator 3 and boosted level generator 4) is provided for the plurality of memory cell array units 21 to 24. At the time of access, a delay time DT12 is given to the output signal lez of the S / A control circuit 10. At the time of the refresh operation, each power supply voltage drops below a predetermined level due to the shortage of current supply capability of the power supply unit (the power supply voltage generator 3 and the boost level generator 4), and the operation speed (change in signal level) decreases. However, the output signal le of the S / A control circuit 10 is adjusted to correspond to this delay.
z is given a delay time DT2 longer than the delay time DT12 at the time of normal access to match the operation timing (delay)
Let it.

As shown in FIG. 11, a plurality of word decoders (word decoder columns) 8 receive a signal pwlz from a word decoder control circuit 7 and a row address to select a predetermined word line WL. It has become. Further, the S / A activation circuit 11 outputs the S / A
The signal lez from the control circuit 10 is received, and a plurality of S /
Signals nsa and psa are supplied to A (S / A column) 12.

The column decoder 9 receives the column address and selects a corresponding S / A 12. Each S / A12
Receives the signals nsa and psa from the S / A activation circuit 11, and receives the corresponding bit lines BL and / BL, respectively.
And a small potential of the memory cell MC provided at the intersection with the word line WL selected by the word decoder 8. The configurations of the sense amplifier activating circuit (S / A activating circuit) 11, the sense amplifier (S / A) 12, and the word decoder 8 are the same as those of the conventional semiconductor memory device described with reference to FIGS. S / A activation circuit 1 in
11, the S / A 112, and the word decoder 108, and the description thereof is omitted.

Next, the refresh operation of the semiconductor memory device of this embodiment will be described. As shown in FIG.
First, when the row address strobe signal / ras changes from the high level “H” to the low level “L”, the output signal brasz (row access signal) of the row control circuit 6 Each of the signals prez is changed from a low level “L” to a high level “H”.
Stand up. Here, during the refresh operation, the control signal refz changes from the low level “L” to the high level “H” at substantially the same timing as the row address strobe signal / ras.

Further, an output signal pwlz (a signal from which the word line WL is raised) of the word decoder control circuit 7 is generated (changes from low level "L" to high level "H"), and S / A control is performed. The signal lez for activating the sense amplifier operation output from the circuit 10 is connected to the resistors R11 and R1.
The signal is delayed from the low level “L” to the high level “H” by being delayed by a predetermined time (delay time DT2) due to 3 to R17 and the capacitors C11 and C13 to C17. here,
The delay time DT2 includes a delay due to the delay circuit 100, and the operation time (voltage drop) of the output voltage of the power supply unit (the power supply voltage generator 3 and the boost level generator 4) is reduced by the delay time DT2. The control timing of the word line WL is synchronized with the delay of the signal level change). At the time of normal access (at the time of reading and writing), the control signal refz is at the low level “L”.
Therefore, the delay circuit 100 is not involved, and the output signal lez of the S / A control circuit 10 includes the delay time DT12.

The output signal prepz of the precharge control circuit 5 receives the signal prez changing to a high level "H" while the signal pwlz is at a high level "H".
The signal rises from the low level “L” to the high level “H” after being delayed by a predetermined time (delay time DT1) by the resistors R51 to R56 and the capacitors C51 to C56. That is,
The precharge control circuit 5 outputs a signal p at a predetermined timing.
repz is generated and returned to the row control circuit 6 to execute a precharge operation. Here, the delay time DT1 includes a delay caused by the delay circuit 50, and the delay time DT1 causes each signal (brasz, pwlz, lez, etc.) to be delayed due to a decrease in the operation speed due to a decrease in the output voltage of the power supply unit.
The timing is synchronized. At the time of normal access, the control signal refz is at the low level “L”, the delay circuit 50 is not involved, and the output signal prepz of the precharge control circuit 5 has a delay time D
T11 will be included.

Further, the row control circuit 6 outputs the signal pr
ez, the output signal brasz is changed from the high level “H” to the low level “L”, and the output signal pwlz of the word decoder control circuit 7 is accordingly changed from the high level “H” to the low level “L”. Change. Also, the signal pw
In response to the change of lz, the signal lez output from the S / A control circuit 10 is connected to the resistors R11, R12, R16, R17.
The signal is delayed from the high level "H" to the low level "L" by being delayed for a predetermined time by the capacitors C11, C12, C16, C17 and the like. At the time of normal access, the control signal refz is at the low level “L”, the delay circuit 100 is not involved, and the signal lez is connected to the resistors R11 and R1.
2 and a delay from the high level "H" to the low level "L" after being delayed by a predetermined time by the capacitors C11 and C12.

As described above, in the semiconductor memory device of the present embodiment, the S / A control circuit 10
Is increased from DT12 to DT2, and the delay time in the precharge control circuit 5 is increased by DT1.
By increasing the length from 1 to DT1, the refresh operation can be adjusted to a delay in operation timing due to insufficient current supply capability (voltage drop) of the power supply unit during the refresh operation, and a plurality of power supply generation circuits are provided. A reliable refresh operation can be performed without increasing the occupied area or power consumption.

That is, according to the semiconductor memory device of the present embodiment, at the time of refreshing, by delaying the signal lez (delaying the sensing operation), the rising of the word line (WL) is caused by the voltage drop (bump down) of the power supply. The sense operation does not start before the data comes out from the memory cell at a later time, and the signal prep
By delaying z, it is possible to prevent the word line from closing when the level difference between the bit lines (BL, / BL) is not sufficient.

FIG. 12 is a circuit diagram showing an example of a control signal generating circuit in the memory cell array portion of FIG.
FIG. 3 is a block diagram showing a memory cell array section and a control signal generation circuit in a semiconductor memory device to which the present invention is applied. As shown in FIG. 12, the control signal generation circuit (refz generation circuit) 13 includes a command recognition unit 30, a plurality of level detection units 31 to 34, and a NOR gate NO.
When the output of the command recognition unit 30 or any of the level detection units 31 to 34 becomes a high level “H”, the control signal is changed from a low level “L” to a high level “H”. It is set up. That is, the logic of each command signal (clock enable signal cke, chip select signal / CE, row address strobe signal / ras, column address strobe signal / cas, and write enable signal WE) and each power supply Recognition is made based on the voltage drop of the voltage (the boost levels VPP1 to VPP4).

As shown in FIG. 12, the command recognition unit 30 includes inverters I31 to I33 and a NAND gate NA.
ND30 and NOR gate NOR30, chip select signal / CE is low level "L", row address strobe signal / ras is low level "L",
When the column address strobe signal / cas is at a low level "L", the write enable signal WE is at a high level "H", and the clock enable signal cke is at a low level "L", a high level "H" signal is output. Is output to the NOR gate NOR3. As shown in FIG. 13, each of the level detectors 31 to 34 includes a booster level VPP1 to VPP4 in each of the memory cell arrays 21 to 24.
Is compared with a reference voltage Vr obtained by dividing the voltage VPP (the output voltage of the boosting level generator 14 dedicated to the control signal generation circuit) by the resistors R311 and R312. For example, the level detection unit 31 Type MOS transistor Q
A differential amplifier circuit composed of P311 and QP312 and N-channel type MOS transistors QN311 to QN313 compares the boosted level VPP1 of the memory cell array 21 with the reference voltage Vr, and sets the boosted level VPP1 to the reference voltage Vr.
When it becomes lower than r, a high level "H" is output to the NOR gate NOR3.

Therefore, the control signal generating circuit 1 shown in FIG.
3 indicates that the control signal refz is set to the high level “H” when the output of the command recognition unit 30 is at the high level “H” or when the output of any of the level detection units 31 to 34 is at the high level “H” The operation timing is synchronized by increasing the delay time of the output signal prepz of the precharge control circuit 5 and the output signal lez of the S / A control circuit 10 described above. The control signal generation circuit 13 shown in FIG. 12 detects the boosted levels VPP1 to VPP4 in each of the memory cell arrays 21 to 24, but detects the normal power supply voltage level and the like to recognize the refresh operation. It may be configured as follows. Further, the semiconductor memory device of the present invention is not limited to a DRAM or an SDRAM, and can be applied to a nonvolatile semiconductor memory device with a refresh operation.

[0049]

As described in detail above, according to the semiconductor memory device of the present invention, a predetermined signal is delayed only at the time of refresh, so that the refresh operation can be performed in accordance with the delay of the operation timing due to the voltage drop at the time of refresh. As a result, a reliable refresh operation can be performed without increasing the occupied area of the power supply unit and increasing power consumption due to the provision of the plurality of power supply generation circuits.

[Brief description of the drawings]

FIG. 1 is a block diagram conceptually showing a memory cell array unit and a power generation circuit in an example of a conventional semiconductor memory device.

FIG. 2 is a block diagram conceptually showing a memory cell array section and a power supply generation circuit in another example of the conventional semiconductor memory device.

FIG. 3 is a block circuit diagram illustrating a main configuration of an example of a conventional semiconductor memory device.

FIG. 4 is a timing chart for explaining a refresh operation of the semiconductor memory device of FIG. 3;

FIG. 5 is a block circuit diagram showing a configuration example of a main part of a memory cell array unit in a conventional semiconductor memory device.

6 is a circuit diagram showing an example of an S / A activation circuit in the memory cell array section of FIG.

FIG. 7 is a circuit diagram showing an example of a word decoder in the memory cell array section of FIG.

FIG. 8 is a block diagram conceptually showing a memory cell array section and a power generation circuit in an example of a semiconductor memory device to which the present invention is applied.

FIG. 9 is a block circuit diagram showing a configuration of a main part in one embodiment of the semiconductor memory device according to the present invention.

FIG. 10 is a timing chart illustrating a refresh operation of the semiconductor memory device of FIG. 9;

FIG. 11 is a block circuit diagram showing a configuration example of a main part of a memory cell array in a semiconductor memory device to which the present invention is applied;

FIG. 12 is a circuit diagram showing an example of a control signal generation circuit in the memory cell array section of FIG.

FIG. 13 is a block diagram showing a memory cell array section and a control signal generation circuit in a semiconductor memory device to which the present invention is applied;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor memory device (memory chip) 3 power supply voltage generator 4 boosted level generator 5 precharge control circuit 6 row control circuit (row control circuit) 7 word decoder control circuit 8 word decoder 9 ... column decoder 10 ... sense amplifier control circuit (S / A control circuit) 11 ... sense amplifier activation circuit (S / A activation circuit) 12 ... sense amplifier (S / A) 13 ... control signal generation circuit (refz generation circuit) 14: boost level generator dedicated to control signal generation circuit 21-24: memory cell array unit 30: command recognition unit 31-34: level detection circuit 50, 100: delay circuit

Claims (13)

[Claims] 1. A semiconductor memory device which involves refreshing a memory cell, wherein a predetermined signal is delayed only at the time of refreshing, so that a refresh operation is performed in accordance with a delay in operation timing due to a voltage drop at the time of refreshing. A semiconductor memory device characterized by doing so. 2. The semiconductor memory device according to claim 1, wherein a voltage drop during said refresh occurs in an output voltage of a power supply voltage generator and an output voltage of a boost level generator. Semiconductor storage device. 3. The semiconductor memory device according to claim 2, wherein said power supply voltage generator and said boosted level generator operate with a common current supply capability during a normal access and a refresh operation. The number of sense amplifiers that operate at the time of refreshing is larger than the number of sense amplifiers that operate at the time of normal access. 4. The semiconductor memory device according to claim 1, wherein said semiconductor memory device has a plurality of memory cell array sections, and when a potential of a boosted level in each of said memory cell array sections becomes lower than a reference level. Wherein the predetermined signal is delayed. 5. The semiconductor memory device according to claim 1, wherein said predetermined signal is delayed by recognizing a refresh operation from the logic of each signal. 6. The semiconductor memory device according to claim 1, wherein the predetermined signals delayed only at the time of refreshing are an output signal of a sense amplifier control circuit and an output signal of a precharge control circuit. Storage device. 7. A power supply unit, and a memory cell array unit to which an output voltage from the power supply unit is supplied. When refreshing memory cells in the memory cell array unit, more sense amplifiers are required than when reading and writing. A semiconductor memory device that operates to reduce an output voltage from the power supply unit, comprising: a control signal generation circuit that detects the refresh operation and generates a control signal; and delays driving of a sense amplifier in response to the control signal. A semiconductor memory device, comprising: a sense amplifier control circuit for causing the word line decoder to receive the control signal and delaying the driving of the word decoder. 8. The semiconductor memory device according to claim 7, wherein said control signal generation circuit detects a refresh operation by comparing a voltage in said memory cell array section with a reference voltage. Semiconductor storage device. 9. The semiconductor memory device according to claim 8, wherein a voltage in said memory cell array unit for detecting said refresh operation is a voltage of a boosted level. 10. The semiconductor memory device according to claim 7, wherein said control signal generation circuit detects a refresh operation from the logic of each signal. 11. A semiconductor memory device having a normal operation mode and a refresh operation mode, wherein the number of word lines selected in the refresh operation mode is larger than that in the normal operation mode. The first time from the transition of the activation signal to the active state to the start of output of the sense amplifier drive signal is equal to the first time from the transition of the activation signal to the active state in the normal operation mode. A semiconductor memory device configured to be longer than a second time until output starts. 12. A semiconductor memory device having a normal operation mode and a refresh operation mode, wherein the number of sense amplifiers activated in the refresh operation mode is larger than in the normal operation mode. A semiconductor memory device, wherein a first sense amplifier activation period is configured to be longer than a second sense amplifier activation period in the normal operation mode. 13. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is
A semiconductor memory device, which is a RAM or a synchronous DRAM.