JPH1173301A - 情報処理装置 - Google Patents
情報処理装置Info
- Publication number
- JPH1173301A JPH1173301A JP9234357A JP23435797A JPH1173301A JP H1173301 A JPH1173301 A JP H1173301A JP 9234357 A JP9234357 A JP 9234357A JP 23435797 A JP23435797 A JP 23435797A JP H1173301 A JPH1173301 A JP H1173301A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- flag
- information
- execution
- information processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30021—Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30058—Conditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9234357A JPH1173301A (ja) | 1997-08-29 | 1997-08-29 | 情報処理装置 |
| US09/143,943 US6282632B1 (en) | 1997-08-29 | 1998-08-31 | Information processor having duplicate operation flags |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9234357A JPH1173301A (ja) | 1997-08-29 | 1997-08-29 | 情報処理装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH1173301A true JPH1173301A (ja) | 1999-03-16 |
| JPH1173301A5 JPH1173301A5 (2) | 2005-06-23 |
Family
ID=16969746
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9234357A Pending JPH1173301A (ja) | 1997-08-29 | 1997-08-29 | 情報処理装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6282632B1 (2) |
| JP (1) | JPH1173301A (2) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8189599B2 (en) * | 2005-08-23 | 2012-05-29 | Rpx Corporation | Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks |
| US7782873B2 (en) * | 2005-08-23 | 2010-08-24 | Slt Logic, Llc | Omni-protocol engine for reconfigurable bit-stream processing in high-speed networks |
| US8825715B1 (en) * | 2010-10-29 | 2014-09-02 | Google Inc. | Distributed state/mask sets |
| US11269661B2 (en) * | 2019-03-04 | 2022-03-08 | Micron Technology, Inc. | Providing, in a configuration packet, data indicative of data flows in a processor with a data flow manager |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4809169A (en) * | 1986-04-23 | 1989-02-28 | Advanced Micro Devices, Inc. | Parallel, multiple coprocessor computer architecture having plural execution modes |
| US5125092A (en) * | 1989-01-09 | 1992-06-23 | International Business Machines Corporation | Method and apparatus for providing multiple condition code fields to to allow pipelined instructions contention free access to separate condition codes |
| JP2832899B2 (ja) * | 1993-05-31 | 1998-12-09 | 松下電器産業株式会社 | データ処理装置およびデータ処理方法 |
| US5625835A (en) * | 1995-05-10 | 1997-04-29 | International Business Machines Corporation | Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor |
| US5805850A (en) * | 1997-01-30 | 1998-09-08 | International Business Machines Corporation | Very long instruction word (VLIW) computer having efficient instruction code format |
-
1997
- 1997-08-29 JP JP9234357A patent/JPH1173301A/ja active Pending
-
1998
- 1998-08-31 US US09/143,943 patent/US6282632B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| US6282632B1 (en) | 2001-08-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6334176B1 (en) | Method and apparatus for generating an alignment control vector | |
| US4449184A (en) | Extended address, single and multiple bit microprocessor | |
| US5996057A (en) | Data processing system and method of permutation with replication within a vector register file | |
| KR100571322B1 (ko) | 파이프라인식 프로세서에서의 예외 취급 방법, 장치 및시스템 | |
| JP2818249B2 (ja) | 電子計算機 | |
| US4539635A (en) | Pipelined digital processor arranged for conditional operation | |
| US6338134B1 (en) | Method and system in a superscalar data processing system for the efficient processing of an instruction by moving only pointers to data | |
| EP3166015A1 (en) | Fetch ahead branch target buffer | |
| CN111782270B (zh) | 一种数据处理方法及装置、存储介质 | |
| EP0094535A2 (en) | Pipe-line data processing system | |
| JP2004529405A (ja) | 依存性を決定するためのコンテンツ・アドレス指定可能メモリを実装したスーパースケーラ・プロセッサ | |
| US8285976B2 (en) | Method and apparatus for predicting branches using a meta predictor | |
| US5349671A (en) | Microprocessor system generating instruction fetch addresses at high speed | |
| US7546442B1 (en) | Fixed length memory to memory arithmetic and architecture for direct memory access using fixed length instructions | |
| US4028670A (en) | Fetch instruction for operand address calculation | |
| CN108959180B (zh) | 一种数据处理方法及系统 | |
| US20020078333A1 (en) | Resource efficient hardware loops | |
| JPH1173301A (ja) | 情報処理装置 | |
| US5446909A (en) | Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand | |
| JP2781779B2 (ja) | 分岐制御回路 | |
| US7415599B1 (en) | Instruction operation and operand memory location determined based on preceding instruction operation and operand memory location | |
| JPS61288230A (ja) | パイプライン制御方式 | |
| JP2843844B2 (ja) | 並列演算処理装置 | |
| JP5263498B2 (ja) | 信号処理プロセッサ及び半導体装置 | |
| JPH06162067A (ja) | ベクトル命令制御装置および制御方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040830 |
|
| RD01 | Notification of change of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7421 Effective date: 20040914 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041005 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050214 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050222 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20050621 |