JPH1174625A - Wiring board and manufacturing method thereof - Google Patents

Wiring board and manufacturing method thereof

Info

Publication number
JPH1174625A
JPH1174625A JP23315797A JP23315797A JPH1174625A JP H1174625 A JPH1174625 A JP H1174625A JP 23315797 A JP23315797 A JP 23315797A JP 23315797 A JP23315797 A JP 23315797A JP H1174625 A JPH1174625 A JP H1174625A
Authority
JP
Japan
Prior art keywords
wiring
insulator
wiring board
width
transfer sheet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23315797A
Other languages
Japanese (ja)
Other versions
JP3085658B2 (en
Inventor
Akihiko Nishimoto
昭彦 西本
Katsura Hayashi
桂 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP09233157A priority Critical patent/JP3085658B2/en
Publication of JPH1174625A publication Critical patent/JPH1174625A/en
Application granted granted Critical
Publication of JP3085658B2 publication Critical patent/JP3085658B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/115Via connections; Lands around holes or via connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/119Details of rigid insulating substrates therefor, e.g. three-dimensional details
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/10Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination

Landscapes

  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】 【課題】欠けや割れ等が発生し難く、絶縁体表面の平坦
度が高く、また、高密度配線基板を作製するために配線
幅を小さくする場合にも配線の絶縁体への密着力が大き
い高性能で高信頼性の配線基板とその製造方法を提供す
る 【解決手段】絶縁体2表面に金属材料による表面配線3
を上面が露出した状態で埋設してなり、上記表面配線3
の平均表面粗さを200nm以上とするとともに、上記表
面配線3の上面幅w1を下面幅w2より大きくして該表
面配線3の断面形状を形成角α°が45°〜80°の逆
台形とする。また、このような配線基板を得るために転
写シート11の表面に形成された金属層13をエッチン
グ処理して断面形状が台形状となる配線を形成し、上記
配線の表面を平均表面粗さ200nm以上に粗化した後、
上記転写シート11を絶縁体2の表面に圧接して、上記
配線を上記絶縁体2表面に転写させる。
(57) [Summary] [PROBLEMS] To prevent the occurrence of chipping or cracking, to achieve high flatness of the surface of an insulator, and to reduce the width of a wiring in order to manufacture a high-density wiring board. Provided is a high-performance and high-reliability wiring board having a large adhesion to a wiring board and a method for manufacturing the wiring board.
Is buried in a state where the upper surface is exposed.
And the upper surface width w1 of the surface wiring 3 is made larger than the lower surface width w2 so that the cross-sectional shape of the surface wiring 3 is inverted trapezoidal with a formation angle α ° of 45 ° to 80 °. I do. Further, in order to obtain such a wiring board, the metal layer 13 formed on the surface of the transfer sheet 11 is subjected to an etching treatment to form a wiring having a trapezoidal cross-sectional shape, and the surface of the wiring has an average surface roughness of 200 nm. After roughening as above,
The transfer sheet 11 is pressed against the surface of the insulator 2 to transfer the wiring to the surface of the insulator 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、例えば半導体素子
収納パッケージなどに用いられる配線基板とその製造方
法に関し、特に、絶縁体表面に微細配線を配した高密度
配線基板及びその製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board used for, for example, a semiconductor device storage package and a method of manufacturing the same, and more particularly to a high-density wiring board having fine wirings arranged on an insulator surface and a method of manufacturing the same. is there.

【0002】[0002]

【従来技術とその課題】従来から、配線基板、例えば、
半導体素子を収納するパッケージに使用される配線基板
として、比較的高密度の配線が可能な多層セラミック配
線基板が多く用いられてきた。この多層セラミック配線
基板は、アルミナなどの絶縁体と、その表面に形成され
たWやMo等の高融点金属からなる配線導体とから構成
されるもので、この絶縁体の一部に凹部が形成され、こ
の凹部内に半導体素子が収納され、蓋体によって凹部を
気密に封止されるものである。
2. Description of the Related Art Conventionally, a wiring board, for example,
2. Description of the Related Art Multilayer ceramic wiring boards capable of relatively high-density wiring have been widely used as wiring boards used for packages containing semiconductor elements. This multilayer ceramic wiring board is composed of an insulator such as alumina and a wiring conductor made of a high melting point metal such as W or Mo formed on the surface thereof, and a concave portion is formed in a part of the insulator. The semiconductor element is housed in the recess, and the recess is hermetically sealed by the lid.

【0003】ところで、多層配線基板や半導体素子収納
用パッケージなどに使用される配線基板は、各種電子機
器の高性能化に伴って、今後益々高密度化が進み、配線
幅や配線ピッチを50μm以下にすることが要求されて
おり、バイアホールもインタースティシャルバイアホー
ル(IVH)にする必要やICチップの実装方法もワイ
ヤーボンディングからフリップチップと代わるため、基
板自体の平坦度を小さくする必要も生じている。しかし
ながら、多層セラミック配線基板では、焼結前のグリー
ンシートにメタライズインクを印刷して、印刷後のシー
トを積層して焼結させて製造するのであるが、その製造
工程において高温での焼成時に焼成収縮が生じるため
に、得られた基板に反り等の変形や寸法のばらつき等が
発生しやすく、そのため回路基板の超高密度化やフリッ
プチップ等のような基板の平坦度に関する厳しい要求に
対して、十分に対応できないなという問題があった。
Meanwhile, wiring boards used for multi-layer wiring boards and packages for housing semiconductor elements, etc., have become more and more dense in the future as the performance of various electronic devices has been improved, and the wiring width and wiring pitch have been reduced to 50 μm or less. It is required that the via hole be an interstitial via hole (IVH), and the mounting method of the IC chip also changes from the wire bonding to the flip chip, so that the flatness of the substrate itself needs to be reduced. ing. However, a multilayer ceramic wiring board is manufactured by printing metallized ink on a green sheet before sintering, and laminating and sintering the printed sheets. Due to the shrinkage, the resulting substrate is liable to be deformed such as warpage or dimensional variation, etc., and therefore, in response to strict requirements regarding ultra-high density of circuit boards and flatness of substrates such as flip chips etc. However, there was a problem that it could not cope sufficiently.

【0004】また、多層セラミック配線基板の別の問題
としては、セラミックスが硬くて脆いという性質を有す
ることから、製造工程または搬送工程において、セラミ
ックスの欠けや割れ等が発生しやすく、その結果、半導
体素子の気密封止性が損なわれることがあるため歩留り
が低い等の問題があった。
Another problem of the multilayer ceramic wiring board is that ceramics are hard and brittle, so that chipping or cracking of the ceramics is likely to occur in a manufacturing process or a transporting process. Since the hermetic sealing of the device may be impaired, there are problems such as low yield.

【0005】これに対してセラミック配線基板以外の配
線基板として、有機樹脂を含む絶縁性基板の表面に銅等
の金属層から成る表面配線を形成した樹脂製配線基板が
用いられている。このような樹脂製配線基板は、セラミ
ック配線基板のような欠けや割れ等の欠点がなく、また
多層化に際しても、焼成のような高温での熱処理を必要
としないという利点を有している。
On the other hand, as a wiring board other than the ceramic wiring board, a resin wiring board is used in which a surface wiring made of a metal layer such as copper is formed on the surface of an insulating substrate containing an organic resin. Such a resin wiring board does not have defects such as chipping or cracking unlike a ceramic wiring board, and has the advantage that heat treatment at a high temperature, such as firing, is not required for multilayering.

【0006】しかしながら、樹脂製配線基板は、一般
に、銅箔等の金属箔を絶縁性基板上に貼り、次いで金属
箔の不要な部分をエッチング法やメッキ法により除去す
るという手段により導体表面配線を形成するものである
ことから、種々の問題があった。
However, a resin wiring board is generally formed by attaching a metal foil such as a copper foil on an insulating substrate, and then removing unnecessary portions of the metal foil by etching or plating. Since it is formed, there are various problems.

【0007】例えば、エッチング等の薬液により、絶縁
性基板が劣化してしまったり、金属箔を用いて形成した
導体表面配線は絶縁性基板表面に載置されているのみで
あるため、この表面配線と絶縁性基板とに密着不良がお
きて両者の界面に空隙が生じ易く、ひいては配線不良に
至り使用不能となるなどの問題があった。また多層化に
あたっては、IVHを形成するのに逐次積層によらねば
ならず、一括積層を行うことができない等の問題があ
る。さらに、導体表面配線により絶縁性基板上に凸部が
形成されるために平坦度も低く、フリップチップ実装に
要求される平坦度を満足するに至っていない。
For example, the insulating substrate is degraded by a chemical such as etching, or the conductor surface wiring formed using a metal foil is only placed on the surface of the insulating substrate. There is a problem that a gap is easily formed at the interface between the two and the insulating substrate due to poor adhesion, which leads to a wiring failure and the use of the substrate becomes impossible. In addition, in forming a multilayer, there is a problem that the sequential lamination must be performed to form the IVH, and a batch lamination cannot be performed. In addition, since the protrusions are formed on the insulating substrate by the conductor surface wiring, the flatness is low, and the flatness required for flip chip mounting has not been satisfied.

【0008】樹脂製の配線基板のこれらの問題のうち、
表面配線と絶縁性基板とに密着不良の問題に対しては導
体表面配線の下面と表面とを黒化処理等の手段により針
状の結晶を成長させることにより粗化し、絶縁体と導体
層との密着力を高める方法が提案されている。
[0008] Among these problems of the wiring board made of resin,
In order to solve the problem of poor adhesion between the surface wiring and the insulating substrate, the lower surface and the surface of the conductor surface wiring are roughened by growing needle-like crystals by means such as blackening treatment, so that the insulator and the conductor layer are not roughened. There has been proposed a method for increasing the adhesiveness of a sheet.

【0009】しかしながら、導体配線の下面と表面とを
粗化して密着力を高める方法は、高密度配線基板を作製
するために配線幅を小さくした場合、配線の密着力が極
端に低下し、基板の長期使用時の信頼性が低下するとい
う問題があった。また、バイアホールに導体ペースト等
をもちいてビアホール導体を形成して層間の導通をとる
場合にも、配線とバイアホール導体の密着力が低下する
という問題があった。
However, the method of increasing the adhesion by roughening the lower surface and the surface of the conductor wiring is to reduce the adhesion of the wiring extremely when the wiring width is reduced in order to produce a high-density wiring board, and There is a problem in that the reliability of the device during long-term use is reduced. Further, even when a via-hole conductor is formed in a via-hole by using a conductive paste or the like to establish conduction between layers, there is a problem that the adhesion between the wiring and the via-hole conductor is reduced.

【0010】このため、高密度配線基板とするために必
要な微細配線、ビアホール導体等を形成した信頼性の高
い基板を作製するのは難しいのが現状であった。
For this reason, it has been difficult at present to produce a highly reliable substrate on which fine wirings, via-hole conductors and the like necessary for forming a high-density wiring substrate are formed.

【0011】また、特開平9−64514号には、表面
配線の転写シートからの剥離の問題を改善することを目
的としたプリント配線板の製造方法に関する発明が記載
されている。この製造方法は、表面配線をなすための金
属層を金属膜上に付設した転写シートから該金属層と金
属膜を絶縁体となるプリプレグに転写して金属層を埋没
形成した後、金属膜のみをソフトエッチングにより除去
することを特徴としたものであった。このようにして形
成されるプリント配線基板は、表面配線の断面形状が矩
形であり、また、転写シートに形成される金属層の表面
が滑らかなものであるが、高密度配線基板を作製するた
めに配線幅を小さくする場合には、配線の密着力が十分
とは言えなかった。
Japanese Patent Application Laid-Open No. 9-64514 discloses an invention relating to a method for manufacturing a printed wiring board for the purpose of improving the problem of peeling of a surface wiring from a transfer sheet. In this manufacturing method, a metal layer for forming surface wiring is transferred from a transfer sheet provided on the metal film to the prepreg serving as an insulator, and the metal layer is buried and formed. Was removed by soft etching. The printed wiring board formed in this way has a rectangular cross-sectional surface wiring and a smooth metal layer formed on the transfer sheet. When the wiring width is reduced, the adhesion of the wiring is not sufficient.

【0012】た、軟質状態の絶縁体(プリプレグ)に配
線を転写することにより、絶縁体表面に配線を埋設する
ことにより配線基板の表面の平滑化が可能であるが、こ
のような配線の断面が矩形である場合、図3に示すよう
に、転写シート20表面の配線21と絶縁体22に圧接
した場合、必然的に配線21の周囲の絶縁体22に変形
が伴うために配線21と絶縁体23との十分な密着性が
得られないという問題があった。
The wiring can be transferred to a soft insulator (prepreg), and the surface of the wiring substrate can be smoothed by embedding the wiring on the surface of the insulator. Is rectangular, as shown in FIG. 3, when the wiring 21 on the surface of the transfer sheet 20 is pressed against the insulator 22, the insulator 22 around the wiring 21 is necessarily deformed. There was a problem that sufficient adhesion with the body 23 could not be obtained.

【0013】[0013]

【発明の目的】上記のような従来技術の問題に鑑み、本
発明は、欠けや割れ等が発生し難く、絶縁体表面の平坦
度が高く、また、高密度配線基板を作製するために配線
幅を小さくする場合にも配線の絶縁体への密着力が大き
い高性能で高信頼性の配線基板とその製造方法を提供す
ることを目的とする。
SUMMARY OF THE INVENTION In view of the above-mentioned problems of the prior art, the present invention is directed to a method for manufacturing a high-density wiring board, in which chipping and cracking are unlikely to occur, the insulator surface has a high flatness, and the wiring density is high. It is an object of the present invention to provide a high-performance and highly-reliable wiring board having a large adhesive strength of a wiring to an insulator even when the width is reduced, and a method for manufacturing the same.

【0014】[0014]

【課題を解決するための手段】本発明者は、前記のよう
な課題について鋭意検討した結果、絶縁体表面に金属材
料による表面配線を上面が露出した状態で埋設してな
り、上記表面配線の平均表面粗さを200nm以上とする
とともに、上面幅が下面幅より大きくなるように該表面
配線の断面形状を形成角α°が45°〜80°の逆台形
とすることによって、微細配線、IVH等を形成した高
密度配線基板において配線の下面及び側面を粗化しても
密着力が低下することなく、むしろ密着力が大幅に向上
し、高性能で高信頼性の基板を得ることができることを
知見した。
As a result of intensive studies on the above-mentioned problems, the present inventor has found that a surface wiring made of a metal material is buried on an insulator surface in a state where the upper surface is exposed. By making the average surface roughness 200 nm or more and forming the cross-sectional shape of the surface wiring into an inverted trapezoid having an angle of formation 45 ° to 80 ° so that the upper surface width is larger than the lower surface width, fine wiring, IVH Even if the lower surface and side surfaces of the wiring are roughened on a high-density wiring board on which a structure is formed, the adhesion is not reduced, but the adhesion is greatly improved, and a high-performance and highly reliable substrate can be obtained. I learned.

【0015】また、このような配線基板を製造する方法
として、転写シートの表面に形成された金属層をエッチ
ング処理して断面形状が台形状となる配線を形成し、上
記配線の表面を平均表面粗さ200nm以上に粗化した
後、上記転写シートを絶縁体の表面に圧接して、上記配
線を上記絶縁体表面に転写させることによって、形成角
α°が45°〜80°で上面幅が下面幅より大きい逆台
形状の断面形状を有する表面配線を上記絶縁体表面に埋
設することを特徴とする配線基板の製造方法が好適であ
ることを見いだした。
Further, as a method of manufacturing such a wiring board, a metal layer formed on the surface of a transfer sheet is subjected to an etching treatment to form a wiring having a trapezoidal cross section, and the surface of the wiring is made to have an average surface. After the surface is roughened to a roughness of 200 nm or more, the transfer sheet is pressed against the surface of the insulator, and the wiring is transferred to the surface of the insulator. It has been found that a method for manufacturing a wiring board characterized by embedding a surface wiring having an inverted trapezoidal cross-sectional shape larger than the lower surface width on the surface of the insulator is suitable.

【0016】[0016]

【発明の実施の形態】以下、本発明の実施形態を図によ
って説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0017】本発明実施形態としての配線基板1を図1
の断面図に示すごとく、この配線基板1は複数の絶縁体
2からなり、該絶縁体2には低抵抗金属を主成分とする
金属材料からなる表面配線3が埋没形成され、さらに該
各表面配線3は、バイアホール3aに充填された上記金
属材料よりなる連結導体3bにより結合している。
FIG. 1 shows a wiring board 1 according to an embodiment of the present invention.
As shown in the cross-sectional view of FIG. 1, the wiring board 1 is composed of a plurality of insulators 2, and a surface wiring 3 made of a metal material containing a low-resistance metal as a main component is buried in the insulator 2; The wiring 3 is connected by a connecting conductor 3b made of the above-described metal material filled in the via hole 3a.

【0018】また、上記表面配線3は、側面4と下面5
が粗面化されて絶縁体2との間でアンカリングを得るこ
とができるようになっているとともに上辺6と横辺7の
形成角α°を鋭角とした逆台形の断面形状を有し、上面
幅w1が下面幅w2より大きくなるように埋設されてい
る。
The surface wiring 3 has a side surface 4 and a lower surface 5.
Is roughened so that anchoring can be obtained with the insulator 2 and has an inverted trapezoidal cross-sectional shape in which the formation angle α ° of the upper side 6 and the horizontal side 7 is acute, It is buried so that the upper surface width w1 is larger than the lower surface width w2.

【0019】なお、前記表面配線3の断面形状におい
て、横辺4と上辺5がなす形成角α°は45°〜80°
で、また、その下面5と側面4の表面粗さが200nm
以上であることが好ましい。このうち、上記形成角α°
として、より望ましくは50°〜75°である。形成角
α°が80°より大きいと配線側面を粗化するのが困難
となり絶縁体2と表面配線3の密着強度が低下する他、
後述の転写シート上の回路パターンをプリプレグに圧着
する際、埋設するのが難しくなる。他方、45°より小
さいと絶縁体2と表面配線3との密着力が不足する恐れ
がある。また、配線の下面5及び側面4の表面粗さは2
00nm以上が良く、望ましくは400nm以上が良
い。表面粗さが200nmより小さいと絶縁体2と表面
配線3の密着強度が不足する恐れがある。
In the cross-sectional shape of the surface wiring 3, the formation angle α ° formed by the lateral side 4 and the upper side 5 is 45 ° to 80 °.
And the lower surface 5 and the side surface 4 have a surface roughness of 200 nm.
It is preferable that it is above. Among them, the formation angle α °
Is more preferably 50 ° to 75 °. When the formation angle α ° is larger than 80 °, it is difficult to roughen the side surface of the wiring, and the adhesion strength between the insulator 2 and the surface wiring 3 is reduced.
When a circuit pattern on a transfer sheet to be described later is pressure-bonded to a prepreg, it becomes difficult to embed the circuit pattern. On the other hand, if it is smaller than 45 °, the adhesion between the insulator 2 and the surface wiring 3 may be insufficient. The surface roughness of the lower surface 5 and the side surface 4 of the wiring is 2
It is preferably at least 00 nm, more preferably at least 400 nm. If the surface roughness is smaller than 200 nm, the adhesion strength between the insulator 2 and the surface wiring 3 may be insufficient.

【0020】前記多層配線基板1を構成する絶縁体2
は、例えば有機樹脂とともに無機フィラー、無機繊維、
有機繊維から選ばれる少なくと1種類以上含む複合材料
等からなる。なお、無機フィラー、無機繊維、有機繊維
は有機樹脂中に合計20〜80体積%の割合で均一に分
散されたものを用いると良い。
An insulator 2 constituting the multilayer wiring board 1
Is, for example, an inorganic filler together with an organic resin, inorganic fibers,
It is made of a composite material containing at least one kind selected from organic fibers. The inorganic filler, the inorganic fiber, and the organic fiber are preferably uniformly dispersed in the organic resin at a ratio of 20 to 80% by volume.

【0021】このような複合材料を構成する有機樹脂と
しては、PPE(ポリフェニレンエーテル樹脂)、BT
レジン(ビスマレイドトリアジン)、エポキシ樹脂、ポ
リイミド樹脂、フッ素樹脂、フェノール樹脂、ポリアミ
ノビスマレイミド等の樹脂からなり、とりわけ原料とし
て室温で液体の熱硬化性樹脂であることが望ましい。
As the organic resin constituting such a composite material, PPE (polyphenylene ether resin), BT
It is made of a resin such as a resin (bismaleide triazine), an epoxy resin, a polyimide resin, a fluororesin, a phenol resin, and a polyaminobismaleimide, and it is particularly preferable that the raw material is a liquid thermosetting resin at room temperature.

【0022】他方、前記無機フィラーとしては、SiO
2 、Al2 3 、ZrO2 、TiO2 、AlN、Si
C、BaTiO3 、SrTiO3 、MgTiO3 、ゼオ
ライト、CaTiO3 、ほう酸アルミニウム等の公知の
材料が使用できる。また、その形状としては球状、針状
など任意のものとすることができる。
On the other hand, as the inorganic filler, SiO 2
2 , Al 2 O 3 , ZrO 2 , TiO 2 , AlN, Si
Known materials such as C, BaTiO 3 , SrTiO 3 , MgTiO 3 , zeolite, CaTiO 3 , and aluminum borate can be used. In addition, the shape can be any shape such as a spherical shape and a needle shape.

【0023】さらに、無機又は有機の繊維としては、ガ
ラス繊維、アラミド繊維、セルロース繊維等があり、織
布、不織布など任意の性状のものを用いれば良い。いず
れにしても、多層配線基板1の強度を高めて高信頼性の
基板とするためには、繊維を含む絶縁体2を少なくとも
1層以上含むことが望ましい。
Further, examples of the inorganic or organic fiber include glass fiber, aramid fiber, cellulose fiber and the like, and any property such as woven fabric and non-woven fabric may be used. In any case, in order to increase the strength of the multilayer wiring board 1 and obtain a highly reliable board, it is desirable to include at least one or more layers of the insulator 2 containing fibers.

【0024】また、上記表面配線を構成する低抵抗金属
材料としては、銅、アルミニウム、金、銀から選ばれる
少なくとも1種を含むことが望ましい。また、回路の必
要に応じて、Ni−Cr等の高抵抗の金属を用いる場合
もある。
It is preferable that the low-resistance metal material forming the surface wiring includes at least one selected from copper, aluminum, gold, and silver. A high-resistance metal such as Ni-Cr may be used as necessary for the circuit.

【0025】次ぎに、図1の多層配線基板1の製造方法
を以下に説明する。
Next, a method of manufacturing the multilayer wiring board 1 of FIG. 1 will be described below.

【0026】まず、多層配線基板1を得るために絶縁体
2を作製する。無機フィラーを用いる場合を例にとる
と、無機質フィラーに液状の有機樹脂加えた絶縁性組成
物を混練機(ニーダ)や3本ロール等の手段によって十
分に混合する。十分に混合されたものを圧延法、押し出
し法、射出法、ドクターブレード法によってシート状に
成形した後、有機樹脂を半硬化させる。絶縁性スラリー
は、好適には、絶縁体を構成する前述したような有機樹
脂と無機フィラーの複合材料に、トルエン、酢酸ブチ
ル、メチルエチルケトン、メタノール、メチルセロソル
ブアセテート、イソプロピルアルコール、メチルイソブ
チルケトン、ジメチルホルムアシド等の溶媒を添加して
所定の粘度を有する流動体からなる。かかる観点から、
スラリーの粘度は、形成方法にもよるが100〜300
0ポイズが適当である。半硬化には、有機樹脂は熱可塑
性樹脂の場合には、加熱下で混合したものを冷却し、熱
硬化性樹脂の場合には、完全固化するに十分な温度より
もやや低い温度に加熱すればよい。また、織布、不織布
を用いる場合には、織布、不織布等の繊維にワニス状の
樹脂を含浸、乾燥させ半硬化のプリプレグの絶縁体2を
作製する。
First, an insulator 2 is manufactured to obtain a multilayer wiring board 1. Taking the case of using an inorganic filler as an example, an insulating composition obtained by adding a liquid organic resin to the inorganic filler is sufficiently mixed by means of a kneader (kneader) or a three-roll mill. A sufficiently mixed material is formed into a sheet by a rolling method, an extrusion method, an injection method, or a doctor blade method, and then the organic resin is semi-cured. The insulating slurry is preferably prepared by adding toluene, butyl acetate, methyl ethyl ketone, methanol, methyl cellosolve acetate, isopropyl alcohol, methyl isobutyl ketone, dimethylform to a composite material of an organic resin and an inorganic filler as described above, which constitutes an insulator. It is composed of a fluid having a predetermined viscosity by adding a solvent such as acid. From this perspective,
The viscosity of the slurry is 100 to 300, depending on the forming method.
0 poise is appropriate. For semi-curing, if the organic resin is a thermoplastic resin, cool the mixture under heating, and in the case of a thermosetting resin, heat the organic resin to a temperature slightly lower than the temperature sufficient for complete solidification. I just need. In the case of using a woven or non-woven fabric, a varnish-like resin is impregnated into fibers such as a woven or non-woven fabric and dried to produce a semi-cured prepreg insulator 2.

【0027】次に、上記のようにして作製した絶縁体2
をなすための半硬化のプリプレグのに対して、打ち抜き
法やレーザー加工により所望のバイアホールを形成して
導体ペーストを充填する。導体ペースト中に配合される
金属粉末としては、銅、アルムニウム、銀、金のうち少
なくとも1種の低抵抗金属からなることが望ましく、有
機溶剤とバインダーを添加しペーストを得ることができ
る。
Next, the insulator 2 manufactured as described above is used.
A desired via hole is formed by punching or laser processing with respect to the semi-cured prepreg for forming the conductive paste, and then filled with a conductive paste. The metal powder to be mixed in the conductor paste is desirably made of at least one low-resistance metal among copper, aluminum, silver, and gold, and a paste can be obtained by adding an organic solvent and a binder.

【0028】そして、この半硬化状の絶縁体2に表面配
線3を形成する。配線回路の形成には、図2(a)に示
すように樹脂フィルムからなる転写シート11の表面に
接着剤を介して銅、金、銀、アルムニウム等から選ばれ
る少なくとも1種、または2種以上の合金からなる金属
箔12を張り合せたものを準備する。この時、銅または
銅を含む合金が最も望ましい。
Then, a surface wiring 3 is formed on the semi-cured insulator 2. In order to form the wiring circuit, as shown in FIG. 2A, at least one or two or more selected from copper, gold, silver, aluminum and the like are provided on the surface of the transfer sheet 11 made of a resin film via an adhesive. A metal foil 12 made of an alloy of the above is laminated. At this time, copper or an alloy containing copper is most desirable.

【0029】次に、図2(b)に示すように所望の回路
パターンによるレジスト層16を付設した後、エッチン
グ法により、図2(c)に示すように該レジスト層16
のある転写シート11上に表面配線を構成するための金
属層13を断面形状が台形状となるように形成する。こ
の時、台形の底辺14と横辺15の形成角β°を45°
〜80°とするには、金属層のエッチング速度を2〜5
0μm/分にするのが良い。また、図2(d)に示すよ
うに金属層13の上面18と側面17の表面粗さを20
0nmとするべく金属層13をギ酸あるいはNaClO
2 、NaOH、Na3 PO4 の混合液等で表面処理す
る。この表面粗さは、粗化速度で制御でき、1μm/分
以上の粗化速度で良好に粗化できる。
Next, after a resist layer 16 having a desired circuit pattern is provided as shown in FIG. 2B, the resist layer 16 is formed by an etching method as shown in FIG.
A metal layer 13 for forming a surface wiring is formed on a transfer sheet 11 having a shape such that the cross-sectional shape becomes trapezoidal. At this time, the formation angle β ° of the base 14 and the side 15 of the trapezoid is 45 °.
In order to achieve the angle of ~ 80 °, the etching rate of the metal layer should be 2-5.
It is good to set it to 0 μm / min. Further, as shown in FIG. 2D, the surface roughness of the upper surface 18 and the side surface 17 of the metal
The metal layer 13 is made of formic acid or NaClO
2 , surface treatment with a mixed solution of NaOH, Na 3 PO 4 and the like. The surface roughness can be controlled by the roughening speed, and the surface can be satisfactorily roughened at a roughening speed of 1 μm / min or more.

【0030】次に、このようにして上記金属層13を付
設した転写シート11を、今度は該金属層13がプリプ
レグ19と対面する向きとしてから、図2(e)に示す
ように転写シート11でプリプレグ19を圧力10〜5
00kg/cm2程度の圧力で印加する。そして、上記
金属層13をプリプレグ19内に残したままで転写シー
ト11を接着層(不図示)とともに剥離することにより
金属層13を転写して表面配線3を埋没形成する。
Next, the transfer sheet 11 provided with the metal layer 13 in this manner is turned to the direction in which the metal layer 13 faces the prepreg 19, and then, as shown in FIG. Prepreg 19 with pressure 10-5
It is applied at a pressure of about 00 kg / cm 2. Then, the transfer sheet 11 is peeled off together with an adhesive layer (not shown) while the metal layer 13 is left in the prepreg 19 to transfer the metal layer 13 and bury the surface wiring 3.

【0031】最後に、このようにして表面配線3を形成
したプリプレグ19を積層して加圧加熱して密着し一体
化して多層配線基板1を作製することができる。
Finally, the prepregs 19 on which the surface wirings 3 are formed as described above are laminated, pressed and heated, adhered and integrated, and the multilayer wiring board 1 can be manufactured.

【0032】上記の製造方法によれば、プリプレグの表
面に転写する配線の断面形状を前記所定の台形形状とす
ることにより、配線をプレプレグ表面に圧接した際に、
配線の周辺のプレプレグの変形が抑制される結果、その
圧力が配線の逆台形の横辺、底辺にわたって、プリプレ
グと圧接される結果、配線の断面が矩形の場合(a)に
比較して配線の絶縁体への密着性を大幅に向上させるこ
とができるのである。
According to the above-described manufacturing method, the cross-sectional shape of the wiring to be transferred to the surface of the prepreg is set to the predetermined trapezoidal shape, so that when the wiring is pressed against the surface of the prepreg,
As a result of suppressing the deformation of the prepreg around the wiring, the pressure is pressed against the prepreg over the horizontal and bottom sides of the inverted trapezoid of the wiring, and as a result, the wiring cross section is rectangular as compared to the case (a). It is possible to greatly improve the adhesion to the insulator.

【0033】なお、本発明の配線基板によれば、絶縁体
の表面に微細で高密度の配線を具備するものであるか
ら、例えば、この配線基板をコア基板とし、その表面に
ブルドアップ法により感光性樹脂からなる絶縁体と、メ
ッキなどの薄膜形成法により形成された配線やビアホー
ル導体を順次積層して、高密度の配線基板を作製するこ
ともできる。
According to the wiring board of the present invention, since fine and high-density wiring is provided on the surface of the insulator, for example, this wiring board is used as a core substrate and the surface thereof is formed by a bull-up method. A high-density wiring board can also be manufactured by sequentially laminating an insulator made of a photosensitive resin and wirings and via-hole conductors formed by a thin film forming method such as plating.

【0034】[0034]

【実施例】BTレジン、PPEまたはポリイミド熱硬化
性樹脂に平均粒径が5μmの球状溶融SiO2 、BaT
iO3 、MgTiO3 、CaTiO3 、アスペクト比5
の針状ほう酸アルミニウムウイスカーを50体積%加
え、これに溶媒として酢酸ブチル、トルエン、MEKを
加え、さらに有機樹脂の硬化を促進させるための触媒を
添加し、攪拌翼が公転および自転する攪拌機により1時
間混合した後、スラリーをドクターブレード法により絶
縁体を構成するための厚さ200μmのシート状のプリ
レグを作製した(表1の試料1〜19)。また、別の絶
縁体としてガラス布、アラミド不織布にBTレジン、P
PE、ポリイミドを50体積%含浸乾燥させ厚さ200
μmの絶縁体を構成するための半硬化のプリプレグを作
製した(表1の試料20〜22)。
EXAMPLE A BT resin, PPE or polyimide thermosetting resin was coated with spherical fused SiO 2 , BaT having an average particle size of 5 μm.
iO 3 , MgTiO 3 , CaTiO 3 , aspect ratio 5
Of aluminum borate whiskers of 50% by volume, butyl acetate, toluene, and MEK as solvents were added thereto, and a catalyst for accelerating the curing of the organic resin was further added. After mixing for a time, a 200-μm-thick sheet-shaped pre-leg for forming an insulator from the slurry by a doctor blade method was produced (Samples 1 to 19 in Table 1). In addition, BT resin, P
PE and polyimide are impregnated and dried at 50% by volume to a thickness of 200
Semi-cured prepregs for forming a μm insulator were prepared (Samples 20 to 22 in Table 1).

【0035】[0035]

【表1】 [Table 1]

【0036】これらのプリプレグを150mm□にカッ
トし、CO2 レーザーにより直径100μmのバイアホ
ールを形成した。このバイアホールに銅−銀合金粉末を
主成分とする銅ペーストをスクリーン印刷により埋め込
んだ。
These prepregs were cut into 150 mm squares, and via holes having a diameter of 100 μm were formed using a CO 2 laser. A copper paste containing copper-silver alloy powder as a main component was embedded in the via hole by screen printing.

【0037】一方、ポリエチレンテレフタレート(PE
T)の転写シート表面に接着剤を塗布して厚み12μm
の電解銅箔を接着した。そして、前記絶縁スラリーをレ
ジストとして前記銅箔の表面に感光性のレジストを塗布
し、ガラスマスクを通して露光してパターンを形成した
後、これを塩化第二鉄溶液中に浸漬して非パターン部を
エッチング除去した。レジスト剥離後、金属層の上面及
び側面を10%のギ酸で処理した。なお、作製した金属
層による配線は底幅が50μm、配線と配線との間隔
(配線ピッチ)が50μm以下の微細なパターンであ
る。
On the other hand, polyethylene terephthalate (PE)
Applying an adhesive to the transfer sheet surface of T)
Was adhered. Then, a photosensitive resist is applied to the surface of the copper foil using the insulating slurry as a resist, and a pattern is formed by exposing through a glass mask, and then immersed in a ferric chloride solution to remove a non-pattern portion. It was removed by etching. After the resist was stripped, the top and side surfaces of the metal layer were treated with 10% formic acid. The wiring formed by the metal layer is a fine pattern having a bottom width of 50 μm and an interval between wirings (wiring pitch) of 50 μm or less.

【0038】そして、表1の条件で上記エッチング処理
し、前記形成角β°の断面形状で金属層を形成し、さら
に表1の粗化速度で金属層を粗面化した後に転写シート
とプリプレグを位置合わせして真空積層機により30k
g/cm2 の圧力で30秒加圧した後、転写フィルムと
接着層のみを剥離して金属層を移転することにより、表
面配線を埋没形成した。最後に、このプリプレグを30
kg/cm2 の圧力で6枚積層し、200℃、5時間加
熱処理して多層配線基板を得た。
Then, the above-mentioned etching treatment was carried out under the conditions shown in Table 1, a metal layer was formed in a cross-sectional shape having the above-mentioned formation angle β °, and after the metal layer was roughened at the roughening rate shown in Table 1, the transfer sheet and the prepreg were formed. 30k by vacuum laminating machine
After pressurizing with a pressure of g / cm 2 for 30 seconds, only the transfer film and the adhesive layer were peeled off, and the metal layer was transferred to bury the surface wiring. Finally, add this prepreg to 30
Six sheets were laminated at a pressure of kg / cm 2 and heat-treated at 200 ° C. for 5 hours to obtain a multilayer wiring board.

【0039】なお、樹脂フィルム上に形成された配線の
角度は配線断面をSEMで観察し測定した。また、配線
下面及び側面の表面粗さは、AFMにより測定した。
The angle of the wiring formed on the resin film was measured by observing the cross section of the wiring with an SEM. The surface roughness of the lower surface and the side surface of the wiring was measured by AFM.

【0040】これらの試料について絶縁体と表面配線の
密着強度を、2mm□のパッドを垂直に引っ張り、荷重
を測定することにより求めた。その結果を表1に示す。
For these samples, the adhesion strength between the insulator and the surface wiring was determined by vertically pulling a 2 mm square pad and measuring the load. Table 1 shows the results.

【0041】表1から明らかなように前記形成角α°
(=β°)は45°〜80°、表面配線の下面及び側面
の最大表面粗さRmax(金属層の上面及び側面の表面
粗さ)を200nm以上とすることにより、密着強度2
kg/mm2 以上の高信頼性の多層基板を得ることがで
きた。
As is clear from Table 1, the formation angle α °
(= Β °) is 45 ° to 80 °, and the maximum surface roughness Rmax of the lower surface and the side surface of the surface wiring (surface roughness of the upper surface and the side surface of the metal layer) is 200 nm or more.
A highly reliable multilayer substrate of kg / mm 2 or more was obtained.

【0042】[0042]

【発明の効果】叙上のように、本発明によれば、絶縁体
の表面に表面配線が埋没形成された構成とすることによ
り、欠けや割れ等が発生し難く、絶縁体表面の平坦度を
高くした配線基板において、表面配線の断面形状を逆台
形としすることによって、微細配線、IVH等を形成し
た高密度配線基板において配線の下面及び側面を粗化し
ても密着力が低下することなく、むしろ密着力が大幅に
向上し、高性能で高信頼性の配線基板を得ることができ
るという優れた効果を奏する。
As described above, according to the present invention, since the surface wiring is buried in the surface of the insulator, chipping and cracking are less likely to occur, and the flatness of the surface of the insulator is reduced. By making the cross-sectional shape of the surface wiring into an inverted trapezoid in the wiring board having a higher height, even if the lower surface and the side surface of the wiring are roughened in a high-density wiring board on which fine wiring, IVH, etc. are formed, the adhesion does not decrease. Rather, an excellent effect is obtained in that the adhesion is greatly improved and a high-performance and highly reliable wiring board can be obtained.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板の断面図である。FIG. 1 is a cross-sectional view of a wiring board according to the present invention.

【図2】(a)〜(e)は図1の配線基板の製造方法を
概略説明するための工程図である。
FIGS. 2A to 2E are process diagrams for schematically explaining a method of manufacturing the wiring board of FIG. 1;

【図3】配線のプリプレグへの圧接時の状態を説明する
ための概略断面図であり(a)は従来法、(b)は本発
明の方法の図である。
FIGS. 3A and 3B are schematic cross-sectional views for explaining a state when a wiring is pressed against a prepreg, wherein FIG. 3A is a diagram of a conventional method and FIG. 3B is a diagram of a method of the present invention.

【符号の説明】[Explanation of symbols]

1 多層配線基板 2 絶縁体 3 表面配線 3a バイアホール 3b 連結導体 4、17 側面 5 下面 6 上辺 7、15 横辺 11 転写シート 12 金属箔 13 金属層 14 底辺 16 レジスト層 18 上面 19 プリプレグ w1 上面幅 w2 下面幅 α° 形成角 DESCRIPTION OF SYMBOLS 1 Multilayer wiring board 2 Insulator 3 Surface wiring 3a Via hole 3b Connecting conductor 4, 17 Side surface 5 Lower surface 6 Upper side 7, 15 Horizontal side 11 Transfer sheet 12 Metal foil 13 Metal layer 14 Bottom 16 Resist layer 18 Upper surface 19 Prepreg w1 Upper surface width w2 Bottom width α ° Forming angle

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁体表面に金属材料による表面配線を上
面が露出した状態で埋設してなり、上記表面配線の平均
表面粗さを200nm以上とするとともに、上記表面配線
の上面幅を下面幅より大きくして該表面配線の断面形状
を形成角α°が45°〜80°の逆台形としてなる配線
基板。
1. A surface wiring made of a metal material is buried on an insulator surface in a state where an upper surface thereof is exposed. The surface wiring has an average surface roughness of 200 nm or more, and an upper surface width of the surface wiring is a lower surface width. A wiring substrate having a larger cross-sectional shape of the surface wiring and an inverted trapezoid having a formation angle α ° of 45 ° to 80 °.
【請求項2】転写シートの表面に形成された金属層をエ
ッチング処理して断面形状が台形状となる配線を形成
し、上記配線の表面を平均表面粗さ200nm以上に粗化
した後、上記転写シートを絶縁体の表面に圧接して、上
記配線を上記絶縁体表面に転写させることによって、形
成角α°が45°〜80°で上面幅が下面幅より大きい
逆台形状の断面形状を有する表面配線を上面が露出した
状態で上記絶縁体表面に埋設することを特徴とする配線
基板の製造方法。
2. A metal layer formed on the surface of a transfer sheet is etched to form a wiring having a trapezoidal cross section, and the surface of the wiring is roughened to an average surface roughness of 200 nm or more. By pressing the transfer sheet against the surface of the insulator and transferring the wiring to the surface of the insulator, the cross-sectional shape of the inverted trapezoid having an angle of formation α of 45 ° to 80 ° and an upper surface width larger than the lower surface width is obtained. A method of manufacturing a wiring board, comprising: burying a surface wiring having the exposed upper surface on the surface of the insulator.
JP09233157A 1997-08-28 1997-08-28 Wiring board and manufacturing method thereof Expired - Fee Related JP3085658B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09233157A JP3085658B2 (en) 1997-08-28 1997-08-28 Wiring board and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09233157A JP3085658B2 (en) 1997-08-28 1997-08-28 Wiring board and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPH1174625A true JPH1174625A (en) 1999-03-16
JP3085658B2 JP3085658B2 (en) 2000-09-11

Family

ID=16950622

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3085658B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044638A (en) * 1999-07-30 2001-02-16 Kyocera Corp Multilayer wiring board and method of manufacturing the same
JP2002204043A (en) * 2000-10-31 2002-07-19 Kyocera Corp Wiring board and method of manufacturing the same
JP2005353660A (en) * 2004-06-08 2005-12-22 Shinko Seisakusho:Kk Multilayer printed circuit board and its manufacturing method
JP2006286724A (en) * 2005-03-31 2006-10-19 Kyocer Slc Technologies Corp Wiring board and manufacturing method thereof
JP2008034722A (en) * 2006-07-31 2008-02-14 Sanyo Electric Co Ltd Circuit board manufacturing method
JP2012235166A (en) * 2012-08-23 2012-11-29 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
WO2014044515A1 (en) * 2012-09-20 2014-03-27 Jumatech Gmbh Method for producing a circuit board element, and circuit board element
US9024207B2 (en) 2008-09-12 2015-05-05 Shinko Electric Industries Co., Ltd. Method of manufacturing a wiring board having pads highly resistant to peeling
US9532462B2 (en) 2009-11-25 2016-12-27 Lg Innotek Co., Ltd. Printed circuit board and manufacturing method thereof
JP2017123464A (en) * 2016-01-08 2017-07-13 恆勁科技股分有限公司Phoenix Pioneer Technology Co.,Ltd. Method of fabricating package substrate

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001044638A (en) * 1999-07-30 2001-02-16 Kyocera Corp Multilayer wiring board and method of manufacturing the same
JP2002204043A (en) * 2000-10-31 2002-07-19 Kyocera Corp Wiring board and method of manufacturing the same
JP2005353660A (en) * 2004-06-08 2005-12-22 Shinko Seisakusho:Kk Multilayer printed circuit board and its manufacturing method
JP2006286724A (en) * 2005-03-31 2006-10-19 Kyocer Slc Technologies Corp Wiring board and manufacturing method thereof
JP2008034722A (en) * 2006-07-31 2008-02-14 Sanyo Electric Co Ltd Circuit board manufacturing method
US9024207B2 (en) 2008-09-12 2015-05-05 Shinko Electric Industries Co., Ltd. Method of manufacturing a wiring board having pads highly resistant to peeling
US9532462B2 (en) 2009-11-25 2016-12-27 Lg Innotek Co., Ltd. Printed circuit board and manufacturing method thereof
JP2012235166A (en) * 2012-08-23 2012-11-29 Shinko Electric Ind Co Ltd Wiring board and manufacturing method of the same
WO2014044515A1 (en) * 2012-09-20 2014-03-27 Jumatech Gmbh Method for producing a circuit board element, and circuit board element
CN104756613A (en) * 2012-09-20 2015-07-01 朱马技术有限公司 Method for producing a circuit board element, and circuit board element
JP2017123464A (en) * 2016-01-08 2017-07-13 恆勁科技股分有限公司Phoenix Pioneer Technology Co.,Ltd. Method of fabricating package substrate

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