JPH1175211A - Camera system and method for generating color video signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate a system design and manufacture for a monitor camera or the like and to facilitate a small sized camera system without the need of provision of a clock system with a different frequency by using an oscillation means that provides an output of a clock signal so as to generate a CCd drive signal and a chrominance signal subcarrier and to obtain a high frequency in the system. SOLUTION: The system is made up of a camera head section and a camera control unit 20, the camera control unit 20 is provided with an oscillation circuit 21 that generates a main clock signal, a chrominance subcarrier wave generating means 71 that outputs sequentially digital carrier data to form a signal with the chrominance subcarrier frequency based on the main clock signal sequentially, and a digital signal processing means 41 that applies signal processing to a CCD output signal as a digital video signal, and a video signal generating means 61 that superimposes a synchronizing signal and digital carrier data on an output of the digital signal processing means 41 and restores the resulting signal into an analog signal to generate an analog composite video signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a camera system such as a surveillance camera having a camera head using a two-dimensional CCD, and a method of forming a color video signal in the camera system.

[0002]

2. Description of the Related Art Today, a television camera using a solid-state image pickup device called a CCD is widely used as a camera head of a surveillance camera or the like because the television camera can be easily downsized and installed. CCD of this camera head
For example, a two-dimensional CCD device having 250,000 pixels is used. A video signal of the NTSC standard is formed by the CCD output of the camera head, and the image is projected on a generally used monitor television. Is often used.

In recent years, in accordance with the improvement of integrated circuit manufacturing technology, not only 250,000 pixels but also 35
CCD with higher resolution, such as 10,000 pixels
Is being used. And, for example, 2
In an imaging circuit using a two-dimensional CCD of 50,000 pixels, a charge signal of each pixel is output at a predetermined timing, and a clock signal of about 10 MHz is used as a CCD driving frequency in order to adjust one horizontal scanning time to the NTSC standard. Required.
For this reason, a reference clock pulse is formed using an oscillation circuit having an oscillation frequency of 10 MHz.

Further, in order to display an image photographed by a camera head on a commonly used monitor television of the NTSC standard, a color composite video signal is formed by signal processing of a CCD output. Input to a monitor device is often performed. In order to form this color composite video signal, two color carriers 180 ° out of phase with 3.58 MHz are required to form the chrominance subcarrier, so that a reference of about 14.3 MHz is required. Oscillation circuits that generate signals are also used in camera systems.

Accordingly, two high-frequency oscillation circuits having different frequencies, such as an oscillation circuit for generating a reference clock pulse for driving a CCD and an oscillation circuit for generating a reference signal for forming a chrominance subcarrier, are used in a monitoring camera or the like. Was built into the camera system. In a camera system using a CCD for 350,000 pixels, an oscillation circuit of about 13.5 MHz is used for a clock for driving the CCD, and about 14.3 MHz for transmitting a reference signal for forming a color signal subcarrier. Oscillation circuit.

[0006]

As mentioned above, the CCD
In a camera system using a camera, a reference clock signal for driving a CCD incorporated in a camera head unit and digitally processing an output signal of the CCD and a reference signal for forming a composite video signal including a color burst signal are used. Since two high-frequency clock systems having different frequencies are required, there is a disadvantage that the circuit configuration is complicated.

In particular, in a surveillance camera system in which images shot by a plurality of camera head units are simultaneously displayed on a single monitor television by splitting the screen, arranging two clock lines not only complicates the circuit configuration but also complicates the circuit configuration. ,
There is a high possibility that signals will affect each other and cause noise.In addition, when signals influence each other, it may be necessary to change the wiring position and perform buffering, which complicates board design. Was sometimes When the buffering process is performed, there is a disadvantage that the circuit scale becomes large and it is difficult to reduce the size of the system.

[0008]

The present invention provides a two-dimensional CCD.
When a color video signal is formed by digital signal processing, a data table storing the value of a sine function is formed in advance, and the data table is sequentially formed by a reference frequency signal for driving a two-dimensional CCD. The sine function data is read out to form digital data forming a chrominance signal subcarrier frequency, and a digital video signal including a synchronizing signal and digital data of the chrominance signal subcarrier frequency are combined to form a digital video signal. A method of forming a color video signal for converting an analog video signal into an analog composite video signal including a color burst signal.

As described above, since the data table storing the value of the sine function is formed in advance, and the digital data for forming the color signal subcarrier having a frequency different from the CCD drive frequency is sequentially formed, the color table for the color signal subcarrier is used. An oscillation circuit is not required, and the formation of the CCD driving signal and the formation of the color burst signal having different frequencies can be performed by using one oscillation circuit for the high frequency clock signal.

Further, the present invention provides a camera head unit incorporating a two-dimensional CCD, a clock signal sent to the camera head unit, and processing of an output signal of the two-dimensional CCD from the camera head unit to produce a color composite video. In a camera system including a camera control unit for forming a signal, the camera control unit includes C
Oscillation means for forming a main clock signal fck having a frequency necessary for a drive pulse of a CD is provided, and chrominance signal subcarrier formation means for sequentially outputting digital carrier data as digital data of a chrominance subcarrier by the main clock signal fck is provided. Digital signal processing means for converting the output signal of the CCD into a digital video signal and performing signal processing such as noise removal, gamma correction, adjustment of a clamp level and a white level, and a vertical and horizontal synchronization with the output of the digital signal processing means A camera system is provided with video signal forming means for forming an analog composite video signal having a color burst signal by superimposing a signal and superimposing digital carrier data to return an analog signal.

As described above, the camera system provided with the color signal subcarrier forming means for sequentially outputting the digital data of the color signal subcarrier having a frequency different from the CCD driving frequency has one oscillation circuit for a high frequency clock signal. As a result, it is possible to form a CCD driving signal and a chrominance signal subcarrier having different frequencies. Further, the present invention provides a plurality of camera heads incorporating a two-dimensional CCD, a synchronization signal transmitted to each of the plurality of camera heads, and an output signal of each CCD output from each camera head. A camera control unit for processing and combining to form a color composite video signal for one screen, wherein the camera control unit provides the camera control unit with a frequency required for a CCD drive pulse in one screen. An oscillation circuit for forming a reference clock signal Fck having a frequency obtained by multiplying the number of images displayed in the horizontal direction, a frequency division of the reference clock signal Fck to form a main clock signal fck required for a CCD drive pulse, and Reference synchronizing signal forming means for forming a vertical and horizontal synchronizing signal by the main clock signal fck, Synchronous processing means for removing a synchronizing signal from each signal output from the digital signal section, and a digital processing means for converting each signal output from each synchronous processing means into a digital video signal according to the number of images to be displayed on one screen. Signal processing means, and switching means for switching the video data output from the plurality of digital signal processing means for each horizontal scanning time and sending each to the memory; A plurality of memories each storing video data from the means, and a reference clock signal Fck.
And a main clock signal fck to a plurality of memories so that the frequency of the read signal is a multiple of the frequency of the write signal, and the memory control means for successively outputting the video data of the plurality of memories successively; and a reference clock signal Fck. A chrominance signal subcarrier forming means for sequentially outputting digital carrier data which is digital data of the chrominance signal subcarrier,
Video signal forming means for forming an analog composite video signal having a color burst signal by superimposing a vertical / horizontal synchronizing signal on video data output from the memory, and superimposing digital carrier data and returning to an analog signal. Camera system.

As described above, the camera system provided with the chrominance signal subcarrier forming means for outputting the digital carrier data of the chrominance signal subcarrier having a frequency different from the CCD driving frequency has one reference clock signal oscillation circuit, The color composite video signal can be formed by forming the different CCD drive signals and the color burst signal and combining the signals output from the plurality of camera head units.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a camera system according to the present invention has four imaging cameras 1 as shown in FIG.
A monitor having camera control units 20 having camera heads 1, 12, 13, and 14 and forming a composite video signal for displaying an image obtained by dividing a monitor screen into four by synthesizing video signals from the respective camera heads It is a camera system.

The camera control unit 20 includes an oscillation circuit 21 for generating a reference clock signal Fck and a reference synchronization signal for forming synchronization signals necessary for the four imaging cameras 11, 12, 13, and 14 serving as camera heads. Signal forming means 23, digital signal processing means for performing digital signal processing on output signals from the respective imaging cameras 11, 12, 13, 14 to form video data
41, 42, 43, and 44; memories 26 and 27 for storing video data; and video signal forming means 61 for synthesizing video data stored in the memories 26 and 27 to form an analog video signal.

An oscillating circuit 21 incorporated in the camera control unit 20 oscillates to transmit a reference clock signal Fck having a frequency twice as high as the driving frequency of the CCD in the CCD cameras used for the imaging cameras 11, 12, 13, 14. circuit
The reference clock signal Fck is input to the reference synchronization signal forming means 23, the memory control means 25, and the video signal forming means 61.

The reference synchronizing signal forming means 23 divides the frequency of the reference clock signal Fck by を to form a main clock signal fck equal to the frequency of the CCD drive pulse, and also generates a vertical synchronizing signal in accordance with the NTSC standard. Signal V
And a horizontal synchronizing signal H. The main clock signal fck, the vertical synchronizing signal V and the horizontal synchronizing signal H
Are the first to fourth imaging cameras 11 to
The imaging camera 14, the first to fourth synchronization processing circuits 31 to 34, the first to fourth digital signal processing means 41 to 44, the first switching means 51 and the second switching means 52 And the memory control means 25.

Accordingly, the first imaging camera 11 to the fourth imaging camera 14 drive the CCD by the main clock signal fck from the reference synchronizing signal forming means 23 to form a video signal by photoelectric conversion, A video signal as a CCD output is output to the camera control unit 20 in accordance with the vertical / horizontal synchronization signal from the forming means 23.

In a system for driving the first imaging camera 11 to the fourth imaging camera 14 using a two-dimensional CCD having 250,000 effective pixels, the main clock signal fck
Is set to 9.534964 MHz, and the reference clock signal Fck is set to 19.069928 MHz. Then, the first imaging camera 11 is connected to the first synchronization processing circuit 31 of the camera control unit 20, and the second imaging camera 12 is connected to the second synchronization processing circuit 32 of the camera control unit 20. Is the third synchronization processing circuit 33 of the camera control unit 20 and the fourth imaging camera
14 is a fourth synchronization processing circuit of the camera control unit 20
Connected to 34.

The respective synchronization processing circuits 31, 32, 33, 34 of the first to fourth synchronization processing circuits 31 to 34 use the vertical / horizontal synchronization signal and the main clock signal from the reference synchronization signal forming means 23. The synchronizing signal is removed from a video signal as a CCD output input from each of the imaging cameras 11, 12, 13, and 14, and the signal is output to each of the digital signal processing units 41, 42, 43, and 44.

The first synchronization processing circuit 31 is connected to the first switching means 51 via the first digital signal processing means 41,
The second synchronization processing circuit 32 is provided with a second digital signal processing means 42.
And the third synchronization processing circuit 33 is connected to the second switching means 52 through the third digital signal processing means 43, and the fourth synchronization processing circuit 34 is connected to the fourth digital processing means 34. It is connected to the second switching means 52 via the signal processing means 44.

The digital signal processing means 41, 42, 43, 44
Is to digitize video signals input from the synchronization processing circuits 31, 32, 33, 34, respectively, adjust the clamp level and the white level, and form digital video data by a luminance signal and a color difference signal. . The first switching means 51 to which the first digital signal processing means 41 and the second digital signal processing means 42 are connected is connected to the first memory 26, and the third digital signal processing means 43 and the fourth digital signal processing means 44 Is connected to the second memory 27, and the first switching means 51 and the second switching means 52 switch the input every one horizontal scanning time to switch to the memories 26 and 27. It sends video data.

Accordingly, when the first imaging camera 11 and the second imaging camera 12 are synchronously outputting the CCD output at the timing of the NTSC standard, the first switching means 51 outputs the first digital signal in the A field. The video data of the first scanning line output from the signal processing means 41 is sent to the first memory 26, and the video data of the third scanning line output from the second digital signal processing means 42 is sent to the first memory 26. Next, the video data of the fifth scanning line output from the first digital signal processing means 41 and the video data of the seventh scanning line output from the second digital signal processing means 42 are sent to the first memory 26. ,
In the B field, the video data of the fourth scanning line output from the second digital signal processing means 42 following the video data of the second scanning line output from the first digital signal processing means 41 is stored in the first memory 26. Then, the video data of the sixth scanning line output from the first digital signal processing means 41 and the video data of the eighth scanning line output from the second digital signal processing means 42 are sent to the first memory 26. , And the video data are sequentially sent to the first memory 26 alternately by one horizontal scanning line.

The third digital signal processing means 43 and the fourth digital signal processing means 43
Second switching means 52 to which digital signal processing means 44 is connected
Similarly to the first switching means 51, the video data from the third digital signal processing means 43 and the video data from the fourth digital signal processing means 44 are alternately sent to the second memory 27 for each horizontal scanning line. Things. The first memory 26 and the second memory 27 use a first-in first-out frame memory, and the timing control of writing and reading is controlled by the memory control means 25. The video data from the first switching means 51 and the second memory 27 are simultaneously controlled by the memory control means 25 to store the video data from the second switching means 52.

The memory control means 25 for controlling the first memory 26 and the second memory 27 includes a reference clock signal Fck output from the oscillation circuit 21, a main clock signal fck output from the reference synchronization signal forming means 23, and a vertical synchronization signal Fck. The main clock signal fck is used as a write clock signal, and this write clock signal is first synchronized with the vertical and horizontal sync signals at the timing of video data.
The data is output to the memory 26 and the second memory 27, and is sequentially stored in the first memory 26 and the second memory 27, respectively, from the video data of the first pixel of the first scanning line.

It is to be noted that the effective range of the image is defined and the first memory 26 and the second memory 27 are stored in the first memory 26 and the second memory 27 except for the video data of the first tens of scanning lines and the video data of the first tens of pixels of each horizontal scanning line. Sometimes it is memorized. When outputting the video data from the first memory 26 and the second memory 27 to the video signal forming means 61 by the memory control means 25, the reference clock signal Fck is used as the read clock signal and the first memory
26 and the second memory 27. Therefore, a read clock signal having a frequency twice as high as the write clock signal is sent to the first memory 26 and the second memory 27, and the read speed is set to twice the write speed.

When outputting the read control signal to the first memory 26 and the second memory 27, the read control signal is output to the first memory 26 and the second memory 27 alternately every half field time. After the reading of the first memory 26 is completed, the reading of the second memory 27 is performed. As described above, the frequency of the read clock signal of the first memory 26 or the second memory 27 is set to twice the frequency of the write clock signal, and the video data for two horizontal scanning lines is read in one horizontal scanning time. If the video signal forming means 61 converts the video signal into an analog video signal, the video image captured by the second imaging camera 12 can be arranged to the right of the video image captured by the first imaging camera 11, and can be stored in the first memory 26. The video data for one field can be read in half field time, and if the video data for one field is read in half field time, the video captured by the first imaging camera 11 can be read. The video captured by the second imaging camera 12 can be arranged in the upper half of the monitor screen.

The video data from the second memory 27 is stored in the first memory 27.
Since the read data is read by the read clock signal having twice the frequency of the write clock signal following the video data of the memory 26 in the same manner, the video data for two horizontal scanning lines is output to the video signal forming means 61 in one horizontal scanning time, and A video signal is formed, the video captured by the fourth imaging camera 14 is arranged to the right of the video captured by the third imaging camera 13 by the video data from the second memory 27, and a half field Outputting the video data for one field stored in the second memory 27 at the time, and arranging the video captured by the third imaging camera 13 and the video captured by the fourth imaging camera 14 in the lower half of the monitor screen Can be.

The video signal forming means 61 comprises a chrominance signal subcarrier forming means 71 for outputting digital carrier data as chrominance signal subcarrier data based on the digital encoder 63 and the reference clock signal Fck, and a digital / analog converting means 65. In addition to the video data from the first memory 26 and the second memory 27, the reference clock signal Fck output from the oscillation circuit 21 and the synchronization signal output from the memory control unit 25 are input.

Then, the digital encoder 63 digitally processes the video data from the first memory 26 and the second memory 27 in accordance with the reference clock signal Fck, and converts the video data of the luminance signal and the color difference signal component from the memory control means 25. The vertical synchronizing signal and the horizontal synchronizing signal are superimposed in accordance with the timing of the video data by the synchronizing signal. A standard video signal is formed, and this digital video signal is output to the digital-to-analog conversion means 65. The digital-to-analog conversion means 65 converts the digital video signal from digital to analog to produce an analog video signal.

Therefore, the analog video signal has an output amplifier 81 as an analog video signal having a video signal and a vertical / horizontal synchronizing signal, and also having a color burst signal based on a color signal subcarrier based on digital carrier data Dsc.
Can be output to The chrominance signal subcarrier forming means 71 includes a data table in which digital values obtained by sampling a plurality of periods of a sine curve as a sine function are recorded, and a chrominance signal subcarrier corresponding to one period of the reference clock signal Fck. It is formed by a phase data memory for storing the phase of fsc, and an arithmetic unit for sequentially adding the phase data and reading out and outputting required data from the data table.

That is, as shown in FIG. 2, a data table of sampling data obtained by dividing a sine curve into, for example, 26 is formed, and a digital value of each point obtained by dividing the sine curve into 26 equal parts is represented by a hexadecimal number. This is stored in the chrominance signal subcarrier forming means 71 as a table. The data table shown in FIG. 2 shows that the peak-to-peak (-1 to +1) of the sine curve is 2
56 divided and the value of each point is changed from 00 [H] to FF
[H] is an 8-bit numerical value.

The phase data memory stores the phase value of the chrominance signal subcarrier fsc corresponding to one cycle of the reference clock signal Fck. In this embodiment, the phase value is a unit corresponding to the division number (sampling number) of the sine curve. As described above, the reference clock signal Fck is set to 19.069928 MHz, and the sine curve is divided into 26. Therefore, the phase value: K = (fsc / Fck) × 26 = 3.579545 × 26 ÷ 19.069928 = 4.88036294631 and this phase value K is stored in the phase data memory.

Further, the arithmetic unit sequentially adds this phase value for each pulse of the reference clock signal Fck, and designates each point of the data table by truncating the decimal point from the addition result of the adder. Table designating circuit and digital encoder
63, the adder is composed of several tens of flip-flops, and the table designating circuit is composed of a plurality of logic gates that perform logical operation on the output of each flip-flop.

Therefore, in this arithmetic unit, if the initial value of the adder is set to 0, this adder stores "4.880336294631" stored in the phase data memory for each pulse of the reference clock signal Fck. Are sequentially added, and FIG.
As shown in the figure, for each pulse of the reference clock signal Fck,
“4.88036294631” and “9.7607258”
9262, "14.6108883893", "19.
52145178245 "and" 24.414014731 "
55 ", 3.28217777686 (29.2821
7767786-26), "8.0016540624"
17 "... Are calculated.

Since this adder is a 26-ary adder that matches the sine curve division number of 26,
When the value exceeds 6, a value obtained by subtracting 26 is calculated, and the phase value K is sequentially calculated in the value range (0 to 26) of the data table. Then, the table designating circuit rounds off the decimal part from the addition result of the adder to obtain an integer, and outputs this integer to the data output circuit as a point value. It is output to the encoder 63 as digital carrier data Dsc.

Accordingly, when the value of the adder is “4.88036294631”, the arithmetic unit outputs the point value “4” and the data output circuit outputs the point value “4”.
"E9 [H]" (see FIG. 2) is output to the digital encoder 63 as the digital carrier data Dsc, and when the value of the adder is "9.7607258262", the table specifying circuit outputs the point value "9". The data output circuit outputs “E9 [H]” to the digital encoder 63. When the value of the adder is “14.61048883893”, the table designation circuit outputs “14” and the data output circuit outputs “61”.
[H] ”and the value of the adder is“ 19.521451 ”.
78245 ", the table designating circuit indicates" 19 ",
The data output circuit outputs “0 [H]”. When the value of the adder is “24.4018473155”, the table designation circuit outputs “24” and the data output circuit outputs “44 [H]”.
Is output, and the value of the adder is “3.2282177778”.
When "6", the table designating circuit outputs "3", the data output circuit outputs "D4 [H]", and the value of the adder is "8.0".
162540622417 ", the table designating circuit outputs" 8 ", the data output circuit outputs" F7 [H] ", and the arithmetic unit outputs five digital data in one cycle of the sine curve. Is output to the digital encoder 63 as digital carrier data Dsc.

The frequency of the sine curve based on digital data is 3.579545 megahertz. Therefore, this digital data is output to the digital encoder 63 as digital carrier data Dsc, and based on the reference clock signal Fck from the oscillation circuit 21, the digital carrier data Dsc is added immediately after the horizontal synchronization signal input from the memory control unit 25. This makes it possible to form a chrominance signal subcarrier by a digital signal.

In the NTSC standard, A field and B field
Since the phase is 180 degrees out of phase with the field, the reciprocal of digital carrier data (logic NO
By outputting T), a color carrier wave of one frame can be formed. Then, if the digital video signal obtained by adding the synchronization signal and the chrominance signal subcarrier to the video signal is converted into an analog signal by the digital / analog conversion means 65, an analog video signal of the NTSC standard can be formed.

In the PAL system, a data table of a cosine curve, which is a cosine function shifted by 90 degrees from the sine curve, is also provided as a data table. Similarly, digital data from this data table is read out. It is possible to form two types of chrominance signal subcarriers, which are two types of signals having the same frequency and shifted by 90 degrees. When forming the data table, the number of divisions (sampling number) of the sine curve and the cosine curve shifted by 90 degrees in phase is not limited to 26, and by increasing the number of divisions N, the reference clock signal Fck The digital carrier data Dsc for forming the chrominance signal subcarrier with higher accuracy can be formed in accordance with the increase in the frequency.

Further, if the number of divisions N is a multiple of 4, data can be read out using a predetermined point value P and a value obtained by adding N / 4 to this point value P, so that one sine curve data table is obtained. In this case, two digital carrier data Dsc (sine curve data and cosine curve data) having a phase shift of 90 degrees can be formed.

As described above, the phase value K is determined by the ratio of the frequency of the reference clock signal Fck to the frequency of the chrominance signal subcarrier fsc. It just needs to be multiplied. The frequency of the reference clock signal Fck is 2
Since the number N of divisions is determined in advance by the number of pixels of the dimensional CCD and the like, the frequency of the reference clock signal Fck and the number N of divisions are determined by each camera control unit 20.

Therefore, the phase value K can be obtained by the following equation: K = (fsc / Fck) × N. For this reason,
When a 350,000 pixel CCD is used, the frequency of the reference clock signal Fck formed by the oscillation circuit 21 is determined to be 27 MHz, and when a 380,000 pixel CCD is used, the frequency of the reference clock signal Fck is set to 28.636363 MHz. By obtaining the phase data and storing it in a nonvolatile memory such as a read-only memory as a phase data memory, it can be used for a surveillance camera system using a two-dimensional CCD having various numbers of pixels.

As described above, the camera control unit 20 forms a digital video signal from video data using the chrominance signal subcarrier and the synchronizing signal by the digital encoder 63, performs signal processing by the digital encoder 63, and then executes the digital encoder 63. The digital video signal output from is input to the digital-to-analog converting means 65. The digital-to-analog converting means 65 converts the digital video signal to an analog video signal, and performs noise removal and appropriate amplification to produce a video signal forming means. It is output from 61.

The analog video signal output from the video signal forming means 61 is further amplified by an output amplifier 81 to a predetermined voltage, and an NTSC standard analog video signal is output from an output terminal 85. Accordingly, the video signal output from the output terminal 85 is input to a normal monitor device to divide the screen into four parts, and the four signals are captured by the first imaging camera 11 to the fourth imaging camera 14.
The video signal is a video signal for simultaneously displaying a plurality of images.

In this camera system, the oscillation circuit 21 forms a reference clock signal Fck having a frequency twice as high as the frequency of the driving pulse for driving the CCDs of the first imaging camera 11 to the fourth imaging camera 14. , This reference clock signal Fck
Is divided by half to form a main clock signal fck necessary for driving the CCD and processing a video signal which is a CCD output, and further forms a vertical synchronizing signal and a horizontal synchronizing signal based on the main clock signal fck. And the reference clock signal F
ck is used to form and synthesize digital carrier data for forming a chrominance signal subcarrier.
Since all the signals of the required frequency are formed by the signals of the predetermined frequency formed by the above, it is possible to prevent the influence of the signals from occurring mutually by routing the clock system of the close frequency.

The camera system shown in FIG. 1 is a system having four imaging cameras as camera head units, and a camera system using one imaging camera in the camera head unit has a CCD. Perform signal processing to apply appropriate digital processing to the output, and convert to N
When forming an analog video signal of the TSC standard, a reference clock signal fck for driving a CCD is formed by an oscillation circuit 21 as an oscillating means, and a CC is generated by the reference clock signal fck.
D to output a video signal from the camera head,
The signal processing is performed by a synchronization processing circuit, a digital signal processing means, and a digital encoder 63, and the clock signal fck of the CCD driving frequency is input to the chrominance signal subcarrier forming means 71, and the chrominance signal subcarrier forming means 71 A digital carrier data Dsc is formed by an arithmetic unit using a table,
The digital carrier data Dsc is combined with the video data from the digital signal processing means by the digital encoder 63,
If the digital-to-analog conversion means 65 performs analog conversion to form a video signal having a chrominance subcarrier, CC
There is no need to use a 14.31818 MHz oscillation circuit for forming a color signal subcarrier other than the oscillation circuit 21 for forming a clock signal of the D drive frequency, and a camera system having a single clock system can be provided. .

Further, the number of imaging cameras as camera heads is not limited to one or four. For example, nine camera heads and three frame memories are provided so that three frame memories are provided in each frame memory. An analog composite video signal that divides one screen into nine parts may be formed by storing a video signal from the camera head unit and setting the read clock to a frequency three times the write clock.

As described above, the reference clock signal Fck used as the read clock of each frame memory is a multiple of the main clock signal fck used as the write clock of each frame memory or the clock for driving the CCD. Although it is possible to simultaneously display images taken by the camera unit, a surveillance camera system that monitors a plurality of screens simultaneously while confirming the content of the image taken by each camera head unit is commonly used as an NTSC system.
In the case of a standard monitor device, it is preferable that a video signal of four-screen display is obtained using about four camera head units.

That is, the four camera heads 11, 12, 13, 14
A camera system that processes and combines the CCD output signals output from the CCD to form a color composite video signal for one screen, forms a reference clock signal Fck having a frequency twice the frequency required for the CCD drive pulse. An oscillation circuit 21 and a reference synchronizing signal forming means 23 for forming a main clock signal fck by dividing the frequency of the reference clock signal Fck by half; and a digital signal for forming a color signal subcarrier frequency fsc based on the reference clock signal Fck. A camera system having a chrominance signal subcarrier forming means 71 for sequentially outputting carrier data includes a plurality of camera heads 11 to 14.
When performing image processing of a video signal photographed in the above, all necessary reference frequency signals can be formed by dividing a single frequency reference clock signal Fck, and a high frequency It is not necessary to provide clock systems with different frequencies, eliminating the adverse effects of the mutual influence of clock signals, and designing and manufacturing a system that displays four images simultaneously as multiple images that make it easy to check each image. It can be easier.

[0050]

According to the first aspect of the present invention, a two-dimensional C
When a color video signal is formed by digital signal processing using a CD, a data table storing values of a sine function is formed in advance, and data of the sine function is sequentially read from the data table by a reference frequency signal for driving the CCD. This method is to read out and form digital carrier data of a chrominance signal subcarrier frequency, synthesize a video signal and digital carrier data to form a digital video signal, and perform analog conversion to form an analog color video signal.

Therefore, it is not necessary to form a CCD driving signal and a chrominance signal subcarrier by using one oscillating means for outputting a clock signal, and it is not necessary to provide a high-frequency clock system having a different frequency in the system. System design and manufacturing are facilitated, and a compact camera system can be easily achieved. The present invention described in claim 2 is:
It has an oscillating means for forming a main clock signal fck having a frequency required for a driving pulse of the CCD, and a chrominance signal subcarrier forming means for sequentially outputting digital data of a chrominance subcarrier frequency fsc based on the main clock signal fck. This is a camera system. Therefore, it is not necessary to form a CCD drive signal and a chrominance signal sub-carrier by using one oscillating means for outputting a clock signal and to provide a high-frequency clock system having a different frequency in the system, thereby facilitating the design and manufacture of the system. Thus, a small camera system such as a surveillance camera system can be easily realized.

According to a third aspect of the present invention, there is provided a camera system which processes and combines CCD output signals output from a plurality of camera heads to form a color composite video signal for one screen. Oh, C
An oscillation circuit for forming a reference clock signal Fck having a frequency which is a multiple of a required frequency of the CD drive pulse, and a reference clock signal F
reference synchronizing signal forming means for dividing ck to form a main clock signal fck, and color signal subcarrier forming means for sequentially outputting digital carry data for forming a chrominance signal subcarrier frequency fsc based on the reference clock signal Fck This is a camera system having

Therefore, when performing image processing of video signals photographed by a plurality of camera heads, it is possible to divide the single-frequency reference clock signal Fck to form all necessary reference frequency signals, and It is not necessary to provide a high-frequency clock system with a different frequency in a system that processes video signals, eliminate the adverse effects of the mutual influence of clock signals, and facilitate the design and manufacture of surveillance camera systems and the like as small systems. Can be.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a camera system according to the present invention.

FIG. 2 is a diagram showing an example of digital carrier data.

FIG. 3 is a diagram showing an example of a comparison between a chrominance signal subcarrier and a reference clock signal.

[Explanation of symbols]

11, 12, 13, 14 Imaging Camera 20 Camera Controller 21 Oscillator 23 Reference Synchronization Signal Forming Unit 25 Memory Control Unit 26, 27 Memory 31, 32, 33, 34 Synchronization Processing Circuit 41, 42, 43, 44 Digital Signal Processing Means 51, 52 Switching means 61 Video signal forming means 63 Digital encoder 65 Digital-to-analog converting means 71 Color signal subcarrier forming means 81 Output amplifier 85 Output terminal

Claims (3)

[Claims] 1. A data table for storing a value of a sine function in advance when an image is captured using a two-dimensional CCD and a color video signal is formed by digital signal processing, and the two-dimensional CCD is driven. The data of the sine function is sequentially read from the data table by the reference frequency signal to form digital data forming a chrominance signal subcarrier frequency, and combined with a digital video signal including a synchronization signal and digital data forming a chrominance signal subcarrier frequency. A digital video signal, and converting the digital video signal into an analog signal to form an analog composite video signal having a color burst signal. 2. A camera head incorporating a two-dimensional CCD, a clock signal being sent to the camera head,
A camera system comprising a camera control unit for processing an output signal of a two-dimensional CCD to form a color composite video signal, wherein the camera control unit forms a main clock signal fck having a frequency required for a CCD drive pulse. Oscillating means, and chrominance signal subcarrier forming means for sequentially outputting digital carrier data which is digital data of chrominance signal subcarriers in accordance with the main clock signal fck, and converts the CCD output signal into a digital video signal. It has digital signal processing means for performing signal processing such as noise removal, γ correction, adjustment of clamp level and white level, and superimposes the vertical and horizontal synchronizing signals on the output of this digital signal processing means, and also superimposes digital carrier data. Return to an analog video signal to provide a color burst signal. Camera system characterized by having a video signal forming means for forming an analog composite video signal having a. 3. A plurality of camera heads incorporating a two-dimensional CCD, a synchronization signal transmitted to each of the plurality of camera heads, and a CC output from each camera head.
A camera control unit for processing and synthesizing each of the output signals of D to form a color composite video signal for one screen. On the other hand, a reference clock signal Fck having a frequency obtained by multiplying the number of images displayed in the horizontal direction on one screen.
And a reference synchronization signal for dividing the reference clock signal Fck to form a main clock signal fck necessary for the CCD drive pulse, and for forming a vertical and horizontal synchronization signal based on the main clock signal fck. Means for removing a synchronization signal from each signal output from each camera head unit, synchronization processing means according to the number of images to be displayed on one screen, and converting each signal from the synchronization processing means into a digital video signal Means for switching the number of video images in the vertical direction to be displayed on one screen, which switches video data output from the plurality of digital signal processing units every horizontal scanning time and sends them to the memory, and A plurality of memories each storing video data from each switching means, and a reference clock signal Fck and a main clock signal fck are output to the plurality of memories. A memory control means for successively outputting the video data of a plurality of memories in succession by making the frequency of the read signal a multiple of the frequency of the write signal; and digital carrier data which is digital data of the chrominance subcarrier by the reference clock signal Fck. And a chrominance signal subcarrier forming means for sequentially outputting the digital burst data, and superimposing the vertical and horizontal synchronizing signals on the digital video data output from the memory, and also superimposing the digital carrier data to return to the analog video signal, so Video signal forming means for forming an analog composite video signal having a signal.