JPH1187647A - Semiconductor integrated circuit device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mount a semiconductor integrated circuit device by using a package of a various state, by incorporating a fuse made of a metal layer formed by using the same manufacturing process as that of a second wiring layer from an uppermost layer of a multilayered wiring layer. SOLUTION: A wiring layer 18 and a fuse 19 are simultaneously formed on a semiconductor substrate 1. In this case, after a metal layer of an aluminum layer or the like is, for example, deposited on the substrate 1 by using a sputtering method, a patterned wiring layer 18 and the fuse 19 are simultaneously formed by using lithography and selectively etching technology. The fuse 19 can be formed of a metal layer made of the same material as that of the layer 18. Since the fuse 19 is the metal layer made of the same material as that of the layer 18 as the same material as that of the layer 18 of a second wiring layer from an uppermost layer of a multilayered wiring layer. Thus, the semiconductor integrated circuit device can be mounted by using a package of various states of the package or the like using a CCB connecting technology.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having a fuse capable of forming a high-performance fuse by an easy manufacturing process. The present invention relates to an integrated circuit device and a method for manufacturing the same.

[0002]

2. Description of the Related Art The present inventors have studied a semiconductor integrated circuit device having a fuse. The following is a technique studied by the present inventors, and the outline is as follows.

That is, a DRAM (Dynamic Random Acc.)
2. Description of the Related Art Some semiconductor integrated circuit devices having a memory system (e.g., ess memory) employ a fuse (fuse element) such as a defect relieving fuse for the purpose of relieving a defect in electrical characteristics of a semiconductor memory. is there.

As the fuse, CCB (Controlled
In the case where a package using a collapse bonding technique is applied, a chrome fuse made of a chromium (Cr) film is used. When a package using a wire bonding connection technique is applied, a metal fuse made of an aluminum film or the like as the uppermost layer of a wiring layer is used. Further, when the total number of wiring layers in the multilayer wiring layer of the semiconductor integrated circuit device is small, a polycrystalline silicon fuse made of a polycrystalline silicon film is used.

As a document describing a semiconductor integrated circuit device having a DRAM, there is, for example, a document described in Japanese Patent Application Laid-Open No. 3-214669.

[0006]

However, the above-mentioned chromium fuse is easy to process because a thin chromium film is used as the fuse, but is mounted on a package using CCB connection technology. However, there is a problem that the range of application is narrow because it is limited only to chips that are used.

Further, since the above-described metal fuse is formed by using the manufacturing process of the power supply wiring layer at the uppermost layer of the wiring layer, current concentrates on the power supply wiring layer, so that the uppermost layer of the chip is formed. Since the thickness of the wiring layer is thick, it is difficult to determine the conditions for cutting the metal fuse having the same thickness.

Further, in the above-mentioned polycrystalline silicon fuse, the polycrystalline silicon film used for the polycrystalline silicon fuse has a low moisture resistance, so that a thin silicon oxide film is formed on the polycrystalline silicon film during patterning. Since it is necessary to perform etching while leaving the film, when performing the etching process in the manufacturing process of the multilayer wiring layer, the accuracy of the etching is reduced and foreign matter is generated due to exposure of the interlayer insulating film and the like. There is a problem.

Furthermore, in order to solve the above-mentioned problem, a manufacturing technique for newly forming a conductive film used for a fuse by a manufacturing process different from a multilayer wiring layer is conceivable, but the manufacturing process is increased. However, problems such as an increase in manufacturing cost and manufacturing time and a decrease in manufacturing yield occur, and it is difficult to put the device into practical use.

An object of the present invention is to provide a semiconductor integrated circuit device having a fuse capable of forming a high-performance fuse by an easy manufacturing process, and a method of manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor integrated circuit device of the present invention has a fuse made of a metal layer formed by using the same manufacturing process as the second wiring layer from the uppermost layer in the multilayer wiring layer.

Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention comprises the steps of: after forming a semiconductor element on a semiconductor substrate, forming a wiring layer and an insulating film which are a part of a multilayer wiring layer on the semiconductor substrate. Forming a fuse and a wiring layer made of a metal layer on the uppermost insulating film of the multilayer wiring layer by the same manufacturing process; and forming an insulating film on the semiconductor substrate, Forming a wiring layer as the uppermost layer of the multilayer wiring layer.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

(First Embodiment) FIGS. 1 to 6 are cross-sectional views showing manufacturing steps of a semiconductor integrated circuit device according to a first embodiment of the present invention. The semiconductor integrated circuit device according to the present embodiment has a DRAM having a capacitor in a memory cell and a fuse. The semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 1, a p-type semiconductor substrate 1 made of, for example, single crystal silicon is prepared, and a MOSFET, which is a component of a DRAM, and a capacitor of a memory cell are formed by using the prior art. .

That is, after a p-type well 2 and an n-type well (not shown) are formed on a p-type semiconductor substrate 1 made of, for example, single crystal silicon, a selective region on the surface of the semiconductor substrate 1 is heated. Oxidize to LOCOS (Local Oxidation
A field insulating film 3 for element isolation made of a silicon oxide film having a silicon (of silicon) structure is formed.

Next, after a gate insulating film 4 made of, for example, a silicon oxide film or the like is formed on the surface of the semiconductor substrate 1, a conductive region is selectively formed on selective regions on the surfaces of the gate insulating film 4 and the field insulating film 3. A gate electrode 5 made of a crystalline silicon film is formed. In this case, a part of the gate electrode 5 serves as a gate electrode as a first gate and also serves as a word line (word line; WL) of the DRAM.

Next, after an insulating film 6 made of a silicon oxide film or the like is formed on the gate electrode 5, a pattern such as the gate electrode 5 is formed by using a lithography technique and a selective etching technique. On the side wall of the electrode 5, a side wall spacer 6a made of a silicon oxide film or the like is formed.

Thereafter, an n-type impurity such as phosphorus is ion-implanted into a region where the surface of the p-type well 2 on the semiconductor substrate 1 is exposed, and is diffused to form an n-type impurity serving as a source and a drain of the MOSFET. Of the semiconductor region 7 is formed.
Although not shown, a p-type impurity such as boron is ion-implanted into a region where the surface of the n-type well on the semiconductor substrate 1 is exposed, and is diffused.
A p-type semiconductor region serving as a source and a drain is formed.

Next, an insulating film 8 is formed on the semiconductor substrate 1. The insulating film 8 is, for example, a silicon oxide film formed by CVD (Ch
After being formed by an emical vapor deposition method, the surface is polished and the surface thereof is flattened to form a flattened insulating film 8. In the planarization process, the surface of the insulating film 8 is, for example, etched back or chemically mechanically polished (CM).
An aspect of flattening by the P) method can be adopted.
Thereafter, a through hole is formed in a selective region of the insulating film 8 by using a lithography technique and a selective etching technique, and then a conductive material such as a conductive polycrystalline silicon film or tungsten is buried in the through hole. A plug (plug) 9 is formed in the hole.

Next, after an insulating film 10 such as a thin silicon oxide film is formed on the semiconductor substrate 1, a through hole is formed in the insulating film 10 on a specific plug 9, and then an aluminum layer or the like is formed. Is formed.
In this case, the wiring layer 11 is a bit line (bit line; BL) of the DRAM.

Next, an insulating film 12 is formed on the semiconductor substrate 1. The insulating film 12 is, for example, a silicon oxide film formed by CVD.
After being formed by the method, the surface is polished and the surface is flattened to form the flattened insulating film 12. In this case, the insulating film 12 is, for example, a PSG (Phospho Silicate Glas) which is a silicon oxide film containing phosphorus.
s) A BPSG (Boro Phospho Silicate Glass) film, which is a silicon oxide film containing boron and phosphorus, or an SOG (Spin On) film that can be formed by a spin coating method.
Glass) film or the like can be applied.

Thereafter, through holes are formed in the insulating film 12 and selective regions of the insulating film 10 thereunder by using a lithography technique and a selective etching technique, and then, for example, conductive polycrystalline silicon or tungsten is formed in the through holes. The plug 13 is formed by embedding the conductive material.

Next, COB (Capacitor) is placed on the semiconductor substrate 1.
A storage node (storage electrode) 14, which is an electrode of a capacitor of a tor over bitline type memory cell, is formed.
The storage node 14 is formed by depositing a conductive polycrystalline silicon film containing an impurity such as phosphorus on the semiconductor substrate 1 by a CVD method and then patterning the film using a lithography technique and a selective etching technique. Form. In this case, the storage node 14
It has a function as a lower electrode of a capacitor which is a capacitor for storing information of a memory cell.

Next, a dielectric film 15 is deposited on the semiconductor substrate 1 including the straight node 14. Dielectric film 15
Are, for example, Si ₃ N ₄ (silicon nitride), Ta ₂
O ₅ (tantalum pentoxide) or PZT which is a ferroelectric film
(Lead zirconate titanate) or the like is deposited. Thereafter, a plate electrode 16 which is an electrode of a capacitor is formed on the semiconductor substrate 1. The plate electrode 16 is formed by depositing a conductive polycrystalline silicon film containing an impurity such as phosphorus on the semiconductor substrate 1 by a CVD method and then patterning the film using a lithography technique and a selective etching technique. I do. In this case, the plate electrode 16
Has a function as an upper electrode of a capacitor which is a capacitance element for storing information of a memory cell.

Next, as shown in FIG. 2, an insulating film 17 is formed on the semiconductor substrate 1 as an interlayer insulating film. After that, through holes (not shown) are formed in selective regions of the insulating film 17 as necessary using a lithography technique and a selective etching technique. The insulating film 17 is formed by, for example, forming a silicon oxide film by a CVD method, polishing the surface, and flattening the surface to form a flattened insulating film 17. The flattening process is performed on the insulating film 1
For example, a mode in which the surface of No. 7 is flattened by, for example, an etch-back method or a CMP method can be adopted. Further, as the insulating film 17, for example, a PSG film which is a silicon oxide film containing phosphorus, a BPSG film which is a silicon oxide film containing boron and phosphorus, or an SOG film which can be formed by a spin coating method is used. it can.

Thereafter, the wiring layer 18 and the fuse 19 are simultaneously formed on the semiconductor substrate 1 (FIG. 3). In this case, a metal layer such as an aluminum layer or a copper layer is deposited on the semiconductor substrate 1 using a sputtering method, and then the patterned wiring layer 18 is formed using a lithography technique and a selective etching technique. And the fuse 19 are formed at the same time. Therefore, the fuse 19 is connected to the wiring layer 1
8 can be a metal layer made of the same material.

Next, an insulating film 20 as an interlayer insulating film is formed on the semiconductor substrate 1 (FIG. 4). Thereafter, the insulating film 2 is formed by using a lithography technique and a selective etching technique.
A through hole (not shown) is formed in the 0 selective region as needed. The insulating film 20 is formed by, for example, forming a silicon oxide film by a CVD method, polishing the surface, and flattening the surface to form the flattened insulating film 20. The flattening treatment may employ a mode in which the surface of the insulating film 20 is flattened by, for example, an etch-back method or a CMP method. The insulating film 20 is, for example, a PSG film which is a silicon oxide film containing phosphorus, a BPSG film which is a silicon oxide film containing boron and phosphorus, or an SOG film which can be formed by a spin coating method.
A film or the like can be applied.

Thereafter, a wiring layer 21 as a power supply wiring layer is formed on the semiconductor substrate 1 (FIG. 5). in this case,
After a thick metal layer such as an aluminum layer or a copper layer is deposited on the semiconductor substrate 1 using a sputtering method, the patterned wiring layer 21 is formed using a lithography technique and a selective etching technique. To form Since the wiring layer 21 is used as a power supply wiring layer, the wiring layer 21 is a thicker wiring layer than the underlying wiring layer 18 and the like.

Next, using a lithography technique and a selective etching technique, a region of the insulating film 20 above the fuse 19 is selectively removed, and a groove 22 is formed in the region (FIG. 6). In this case, the groove 22 above the fuse 19 can be easily cut by a simple cutting process when the fuse 19 is cut as required in a prober test or the like. It is for.

FIG. 7 is a plan layout diagram of the fuse 19 and the wiring layer 21 as a power supply wiring layer corresponding to the semiconductor integrated circuit device of the present embodiment shown in FIG. FIG.
Corresponds to a cross-sectional view showing a cross section taken along the line AA in FIG.

FIG. 8 is a plan layout diagram of the fuse 19 and the wiring layer 21 as a power supply wiring layer in the chip 23 of the semiconductor integrated circuit device of the present embodiment. As shown in FIG. 8, each fuse 19 in the chip 23 of the semiconductor integrated circuit device of the present embodiment is arranged corresponding to each of the wiring layers 21 as power supply wiring layers. In another embodiment of the present embodiment, each fuse 19 in the chip 23 can be configured to be arranged corresponding to only a specific one of the wiring layers 21 as a power supply wiring layer.

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the fuse 19 made of a metal layer is used.
Is formed at the same time as the wiring layer 18, the fuse 19 can be formed using an easy manufacturing process. Therefore, a manufacturing process for forming a new metal layer for forming the fuse 19 can be omitted. 19 can reduce the processing conditions at the time of manufacturing. As a result, the high-performance and highly reliable fuse 19 can be manufactured by an easy manufacturing process, and the manufacturing yield can be improved.

The fuse 19 according to the present embodiment is a metal layer of the same layer as the wiring layer 18 which is the second wiring layer from the uppermost layer in the multilayer wiring layer, and is formed of the same material as the wiring layer 18. Since the layer is a layer, the fuse 19 can be easily cut by a simple cutting process when the fuse 19 is cut as necessary in a prober inspection or the like.

Further, the fuse 19 of this embodiment is
This is a metal layer of the same layer as the wiring layer 18 which is the second wiring layer from the uppermost layer in the multilayer wiring layer, and is a metal layer made of the same material as that of the wiring layer 18. The device can be mounted using various types of packages such as a package using the CCB connection technology or a package using the wire bonding connection technology. When mounting, a package according to the design specifications is applied. can do.

(Embodiment 2) FIGS. 9 to 12 are sectional views showing manufacturing steps of a semiconductor integrated circuit device according to Embodiment 2 of the present invention. The semiconductor integrated circuit device of the present embodiment has a DRAM having a capacitor in a memory cell and a fuse, as in the first embodiment. The semiconductor integrated circuit device and the method of manufacturing the same according to the present embodiment will be specifically described with reference to FIG.

First, as shown in FIG. 9, the process of manufacturing the semiconductor integrated circuit device of the first embodiment described above (the process of manufacturing the semiconductor integrated circuit device of the first embodiment described with reference to FIGS. 1 and 2) After a MOSFET is formed on the semiconductor substrate 1 using the same manufacturing process as above, after forming the wiring layer 11 and the capacitor on the semiconductor substrate 1,
An insulating film 17 is formed.

After that, a wiring layer 18 is formed on the semiconductor substrate 1. In this case, a metal layer such as an aluminum layer or a copper layer is deposited on the semiconductor substrate 1 using a sputtering method, and then the patterned wiring layer 18 is formed using a lithography technique and a selective etching technique.
To form

Next, an insulating film 20 as an interlayer insulating film is formed on the semiconductor substrate 1 (FIG. 10). After that, through holes (not shown) are formed in selective regions of the insulating film 20 as necessary using a lithography technique and a selective etching technique. This manufacturing process uses the same manufacturing process as in the first embodiment.

Thereafter, a wiring layer 21 as a power supply wiring layer and a metal layer 21a for forming a fuse are simultaneously formed on the semiconductor substrate 1 (FIG. 11). In this case, a metal layer such as an aluminum layer or a copper layer is deposited with a thick film on the semiconductor substrate 1 by using a sputtering method, and then patterned by using a lithography technique and a selective etching technique. The wiring layer 21 and the metal layer 21a for forming the fuse are simultaneously formed.
Since the wiring layer 21 is used as a power supply wiring layer,
The wiring layer is thicker than the lower wiring layer 18 and the like.

Next, the surface layer of the metal layer 21a for forming a fuse is selectively removed by using a lithography technique and a selective etching technique, and the metal layer 21a is formed.
Of the metal layer in a thin film state having a thickness smaller than the thickness of the wiring layer 21 as the power supply wiring layer by reducing the thickness of the fuse to about half (the same shape as the fuse 19 in the first embodiment described above). Is formed (FIG. 12). Therefore, the fuse 19 is connected to the wiring layer 21 as a power supply wiring layer.
And a metal layer in a thinner state than the wiring layer 21. As a result, the fuse 19 in the thin film state can be easily cut by a simple cutting process when the fuse 19 is cut as required in a prober inspection or the like.

In this case, the plan layout diagram of the fuse 19 and the wiring layer 21 as the power supply wiring layer corresponding to the semiconductor integrated circuit device of the present embodiment shown in FIG. (FIG. 7).

The plane layout of the fuse 19 and the wiring layer 21 as a power supply wiring layer in the chip 23 of the semiconductor integrated circuit device of the present embodiment is the same as the plane layout of the first embodiment (FIG. 8). Is the same as

According to the method of manufacturing a semiconductor integrated circuit device of the present embodiment, the fuse 19 made of a metal layer is used.
Is formed by diverting the manufacturing process of the wiring layer 21 which is the uppermost layer of the multilayer wiring layer, the fuse 19 can be formed using an easy manufacturing process.
The manufacturing process for forming a new metal layer for forming the fuse 19 can be omitted, and the processing conditions at the time of manufacturing the fuse 19 can be relaxed. As a result, the high-performance and highly reliable fuse 19 can be manufactured by an easy manufacturing process, and the manufacturing yield can be improved.

The fuse 19 of the present embodiment is a metal layer of the same layer as the uppermost wiring layer 21 in the multilayer wiring layer (a metal layer in a thinner state than the wiring layer 21), and is the same as the wiring layer 21. Since it is a metal layer made of the above material, the fuse 1
When the fuse 9 is cut, the fuse 19 can be easily cut by a simple cutting process.

Further, the fuse 19 of this embodiment is
Since the metal layer is the same metal layer as the uppermost wiring layer 21 in the multilayer wiring layer and is made of the same material as the wiring layer 21, the semiconductor integrated circuit device of the present embodiment uses the CCB connection technology. Since it can be mounted using various forms of packages such as used packages or packages using wire bonding connection technology,
At the time of mounting, a package according to the design specification can be applied.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, the fuse of the semiconductor integrated circuit device of the present invention can be applied to a fuse for various uses such as a case where a circuit for timing compensation or the like is bypassed by a fuse for repairing a defect or a fuse.

The present invention also relates to a MOSFET, a CMOS,
DR with FET, BiCMOSFET, etc. as constituent elements
The present invention can be applied to a semiconductor integrated circuit device having a memory system such as an AM or SRAM (Static Random Access Memory) and a method of manufacturing the same.

Further, the present invention relates to a MOSFET, a CMO
The present invention can be applied to various semiconductor integrated circuit devices such as a logic system including SFETs, BiCMOSFETs, bipolar transistors, and the like as components, and a method of manufacturing the same.

[0053]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, since the fuse formed of the metal layer is formed simultaneously with the second wiring layer from the uppermost layer in the multilayer wiring layer, the fuse can be formed using an easy manufacturing process. Can be formed, the manufacturing process for forming a new metal layer for forming the fuse can be omitted, and the processing conditions at the time of manufacturing the fuse can be eased. As a result, a high-performance and highly-reliable fuse can be manufactured by an easy manufacturing process, and the manufacturing yield can be improved.

(2). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, since the fuse formed of the metal layer is formed by diverting the manufacturing process of the wiring layer that is the uppermost layer of the multilayer wiring layer, an easy manufacturing process can be used. Therefore, the manufacturing process for forming a new metal layer for forming the fuse can be omitted, and the processing conditions at the time of manufacturing the fuse can be reduced. As a result, a high-performance and highly-reliable fuse can be manufactured by an easy manufacturing process, and the manufacturing yield can be improved.

(3). The fuse according to the present invention is a wiring layer that is the second wiring layer from the uppermost wiring layer in the multilayer wiring layer or a metal layer of the same layer as the uppermost wiring layer, and is a metal layer made of the same material as the wiring layer. Accordingly, the fuse can be easily cut by a simple cutting process when the fuse is cut as required in a prober test or the like.

(4). The fuse according to the present invention is a wiring layer that is the second wiring layer from the uppermost wiring layer in the multilayer wiring layer or a metal layer of the same layer as the uppermost wiring layer, and is a metal layer made of the same material as the wiring layer. Accordingly, the semiconductor integrated circuit device of the present invention can be mounted using various types of packages such as a package using the CCB connection technology or a package using the wire bonding connection technology. A package according to the design specification can be applied.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention;

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 3 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 4 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 5 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 6 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the first embodiment of the present invention;

7 is a plan layout view of a fuse and a wiring layer as a power supply wiring layer corresponding to the semiconductor integrated circuit device shown in FIG. 6;

FIG. 8 is a plan layout diagram of a fuse and a wiring layer as a power supply wiring layer in the chip of the semiconductor integrated circuit device according to the first embodiment of the present invention;

FIG. 9 is a sectional view illustrating a manufacturing process of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 10 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 11 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

FIG. 12 is a sectional view illustrating a manufacturing step of the semiconductor integrated circuit device according to the second embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 well 3 field insulating film 4 gate insulating film 5 gate electrode 6 insulating film 6a sidewall spacer 7 semiconductor region 8 insulating film 9 plug 10 insulating film 11 wiring layer 12 insulating film 13 plug 14 storage node 15 dielectric film DESCRIPTION OF SYMBOLS 16 Plate electrode 17 Insulating film 18 Wiring layer 19 Fuse 20 Insulating film 21 Wiring layer 21a Metal layer 22 Groove 23 Chip

Claims (8)

[Claims] 1. A semiconductor integrated circuit device having a fuse formed of a metal layer formed by using the same manufacturing process as the second wiring layer from the uppermost wiring layer in a multilayer wiring layer. 2. A fuse comprising a metal layer made of the same material as the wiring layer in the same layer as the uppermost wiring layer in the multilayer wiring layer, wherein the thickness of the fuse is smaller than the thickness of the wiring layer. A semiconductor integrated circuit device characterized by being thin. 3. The semiconductor integrated circuit device according to claim 1, wherein said uppermost wiring layer is a power supply wiring layer. 4. The semiconductor integrated circuit device according to claim 1, wherein said fuse is applied to a memory-based semiconductor integrated circuit device. apparatus. 5. A step of forming a wiring layer and an insulating film that are part of a multilayer wiring layer on the semiconductor substrate after forming a semiconductor element on the semiconductor substrate; and forming an uppermost insulating film of the multilayer wiring layer. Forming a fuse and a wiring layer made of a metal layer by the same manufacturing process, and forming an insulating film on the semiconductor substrate, and then forming the uppermost layer of a multilayer wiring layer on the insulating film. Forming a wiring layer as described above. 6. A step of forming a wiring layer and an insulating film which are a part of a multilayer wiring layer on the semiconductor substrate after forming a semiconductor element on the semiconductor substrate; and forming an uppermost insulating film of the multilayer wiring layer. Forming a fuse and a wiring layer made of a metal layer by the same manufacturing process, and a step of making the thickness of the fuse thinner than the thickness of the wiring layer in the same layer as the fuse. A method for manufacturing a semiconductor integrated circuit device. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the uppermost wiring layer is a power supply wiring layer. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 5, wherein said fuse is applied to a memory-based semiconductor integrated circuit device. A method for manufacturing a semiconductor integrated circuit device.