JPS4879984A - - Google Patents
Info
- Publication number
- JPS4879984A JPS4879984A JP47126821A JP12682172A JPS4879984A JP S4879984 A JPS4879984 A JP S4879984A JP 47126821 A JP47126821 A JP 47126821A JP 12682172 A JP12682172 A JP 12682172A JP S4879984 A JPS4879984 A JP S4879984A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q10/00—Administration; Management
- G06Q10/04—Forecasting or optimisation specially adapted for administrative or management purposes, e.g. linear programming or "cutting stock problem"
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/06—Power analysis or power optimisation
Landscapes
- Engineering & Computer Science (AREA)
- Business, Economics & Management (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Human Resources & Organizations (AREA)
- Economics (AREA)
- Strategic Management (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- General Business, Economics & Management (AREA)
- Quality & Reliability (AREA)
- Tourism & Hospitality (AREA)
- Operations Research (AREA)
- Game Theory and Decision Science (AREA)
- Marketing (AREA)
- Development Economics (AREA)
- Entrepreneurship & Innovation (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US21414371A | 1971-12-30 | 1971-12-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS4879984A true JPS4879984A (ja) | 1973-10-26 |
Family
ID=22797942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP47126821A Pending JPS4879984A (ja) | 1971-12-30 | 1972-12-19 |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JPS4879984A (ja) |
| DE (1) | DE2259726A1 (ja) |
| GB (1) | GB1352988A (ja) |
| IT (1) | IT972512B (ja) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116558A (ja) * | 1984-07-03 | 1986-01-24 | Sharp Corp | Ｌｓｉのパツド配置方法 |
| JPS63250152A (ja) * | 1987-04-07 | 1988-10-18 | Nec Corp | 半導体集積回路のレイアウト方法 |
| JPH0614321B2 (ja) * | 1989-10-23 | 1994-02-23 | ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド | プログラム化されたコンパイラを用いたデジタル信号プロセサの実現化方法 |
| JPH06140514A (ja) * | 1992-10-23 | 1994-05-20 | Rohm Co Ltd | 論理回路の設計方法 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4698760A (en) * | 1985-06-06 | 1987-10-06 | International Business Machines | Method of optimizing signal timing delays and power consumption in LSI circuits |
-
1972
- 1972-10-02 GB GB4530272A patent/GB1352988A/en not_active Expired
- 1972-12-06 DE DE2259726A patent/DE2259726A1/de active Pending
- 1972-12-19 IT IT33109/72A patent/IT972512B/it active
- 1972-12-19 JP JP47126821A patent/JPS4879984A/ja active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6116558A (ja) * | 1984-07-03 | 1986-01-24 | Sharp Corp | Ｌｓｉのパツド配置方法 |
| JPS63250152A (ja) * | 1987-04-07 | 1988-10-18 | Nec Corp | 半導体集積回路のレイアウト方法 |
| JPH0614321B2 (ja) * | 1989-10-23 | 1994-02-23 | ブイ・エル・エス・アイ・テクノロジー・インコーポレイテッド | プログラム化されたコンパイラを用いたデジタル信号プロセサの実現化方法 |
| JPH06140514A (ja) * | 1992-10-23 | 1994-05-20 | Rohm Co Ltd | 論理回路の設計方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2259726A1 (de) | 1973-07-12 |
| IT972512B (it) | 1974-05-31 |
| GB1352988A (en) | 1974-05-15 |