JPS51140521A - Address exchange device - Google Patents

Address exchange device

Info

Publication number
JPS51140521A
JPS51140521A JP50065776A JP6577675A JPS51140521A JP S51140521 A JPS51140521 A JP S51140521A JP 50065776 A JP50065776 A JP 50065776A JP 6577675 A JP6577675 A JP 6577675A JP S51140521 A JPS51140521 A JP S51140521A
Authority
JP
Japan
Prior art keywords
exchange device
address exchange
address
accomplish
combining
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50065776A
Other languages
English (en)
Other versions
JPS5760709B2 (ja
Inventor
Naoya Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP50065776A priority Critical patent/JPS51140521A/ja
Publication of JPS51140521A publication Critical patent/JPS51140521A/ja
Publication of JPS5760709B2 publication Critical patent/JPS5760709B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
JP50065776A 1975-05-30 1975-05-30 Address exchange device Granted JPS51140521A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50065776A JPS51140521A (en) 1975-05-30 1975-05-30 Address exchange device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50065776A JPS51140521A (en) 1975-05-30 1975-05-30 Address exchange device

Publications (2)

Publication Number Publication Date
JPS51140521A true JPS51140521A (en) 1976-12-03
JPS5760709B2 JPS5760709B2 (ja) 1982-12-21

Family

ID=13296762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50065776A Granted JPS51140521A (en) 1975-05-30 1975-05-30 Address exchange device

Country Status (1)

Country Link
JP (1) JPS51140521A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109403A (ja) * 1987-10-09 1989-04-26 Instron Corp 複数の制御要素の相互作用的制御を行なうための回路
JPH0251755A (ja) * 1988-06-07 1990-02-21 Bull Hn Inf Syst Inc キャッシュ・メモリーアクセス用仮想／実アドレス変換装置
JPWO2008155851A1 (ja) * 2007-06-20 2010-08-26 富士通株式会社 演算処理装置、エントリ制御プログラムおよびエントリ制御方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01109403A (ja) * 1987-10-09 1989-04-26 Instron Corp 複数の制御要素の相互作用的制御を行なうための回路
JPH0251755A (ja) * 1988-06-07 1990-02-21 Bull Hn Inf Syst Inc キャッシュ・メモリーアクセス用仮想／実アドレス変換装置
JPWO2008155851A1 (ja) * 2007-06-20 2010-08-26 富士通株式会社 演算処理装置、エントリ制御プログラムおよびエントリ制御方法
JP4812876B2 (ja) * 2007-06-20 2011-11-09 富士通株式会社 演算処理装置および演算処理装置の制御方法
US8688952B2 (en) 2007-06-20 2014-04-01 Fujitsu Limited Arithmetic processing unit and control method for evicting an entry from a TLB to another TLB

Also Published As

Publication number Publication date
JPS5760709B2 (ja) 1982-12-21

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