JPS51163867U - - Google Patents

Info

Publication number
JPS51163867U
JPS51163867U JP1975084506U JP8450675U JPS51163867U JP S51163867 U JPS51163867 U JP S51163867U JP 1975084506 U JP1975084506 U JP 1975084506U JP 8450675 U JP8450675 U JP 8450675U JP S51163867 U JPS51163867 U JP S51163867U
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1975084506U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1975084506U priority Critical patent/JPS51163867U/ja
Publication of JPS51163867U publication Critical patent/JPS51163867U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07311—Treating the bonding area before connecting, e.g. by applying flux or cleaning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Die Bonding (AREA)
JP1975084506U 1975-06-19 1975-06-19 Pending JPS51163867U (2)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1975084506U JPS51163867U (2) 1975-06-19 1975-06-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1975084506U JPS51163867U (2) 1975-06-19 1975-06-19

Publications (1)

Publication Number Publication Date
JPS51163867U true JPS51163867U (2) 1976-12-27

Family

ID=28566606

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1975084506U Pending JPS51163867U (2) 1975-06-19 1975-06-19

Country Status (1)

Country Link
JP (1) JPS51163867U (2)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776848A (en) * 1980-10-30 1982-05-14 Seiko Epson Corp Mounting method for integrated circuit chip
JPS60163447A (ja) * 1984-01-17 1985-08-26 ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体素子

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4925976A (2) * 1972-04-05 1974-03-07
JPS4911661B1 (2) * 1969-12-22 1974-03-19

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4911661B1 (2) * 1969-12-22 1974-03-19
JPS4925976A (2) * 1972-04-05 1974-03-07

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5776848A (en) * 1980-10-30 1982-05-14 Seiko Epson Corp Mounting method for integrated circuit chip
JPS60163447A (ja) * 1984-01-17 1985-08-26 ローベルト・ボツシユ・ゲゼルシヤフト・ミツト・ベシユレンクテル・ハフツング 半導体素子

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