JPS5165566A - - Google Patents

Info

Publication number
JPS5165566A
JPS5165566A JP49138371A JP13837174A JPS5165566A JP S5165566 A JPS5165566 A JP S5165566A JP 49138371 A JP49138371 A JP 49138371A JP 13837174 A JP13837174 A JP 13837174A JP S5165566 A JPS5165566 A JP S5165566A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP49138371A
Other languages
Japanese (ja)
Inventor
Osamu Yugawa
Susumu Okikawa
Atsushi Sasayama
Tomio Yamada
Hiroshi Mikino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP49138371A priority Critical patent/JPS5165566A/ja
Publication of JPS5165566A publication Critical patent/JPS5165566A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5449Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP49138371A 1974-12-04 1974-12-04 Pending JPS5165566A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP49138371A JPS5165566A (en) 1974-12-04 1974-12-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49138371A JPS5165566A (en) 1974-12-04 1974-12-04

Publications (1)

Publication Number Publication Date
JPS5165566A true JPS5165566A (en) 1976-06-07

Family

ID=15220360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP49138371A Pending JPS5165566A (en) 1974-12-04 1974-12-04

Country Status (1)

Country Link
JP (1) JPS5165566A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123162A (en) * 1984-11-20 1986-06-11 Toshiba Corp Lead frame for resin seal type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61123162A (en) * 1984-11-20 1986-06-11 Toshiba Corp Lead frame for resin seal type semiconductor device

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