JPS5184530A - Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu - Google Patents

Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu

Info

Publication number
JPS5184530A
JPS5184530A JP50147533A JP14753375A JPS5184530A JP S5184530 A JPS5184530 A JP S5184530A JP 50147533 A JP50147533 A JP 50147533A JP 14753375 A JP14753375 A JP 14753375A JP S5184530 A JPS5184530 A JP S5184530A
Authority
JP
Japan
Prior art keywords
handotaidebaisu
chokusetsutekitesutookanonishita
areino
memori
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50147533A
Other languages
Japanese (ja)
Other versions
JPS5415650B2 (en
Inventor
Aaru Kabarieri Josefu
Jei Haaree Uiriamu
Pii Muurufuerudo Hansu
Robaatashio Rotsuko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/534,605 external-priority patent/US3961251A/en
Priority claimed from US05/534,608 external-priority patent/US3961254A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5184530A publication Critical patent/JPS5184530A/en
Publication of JPS5415650B2 publication Critical patent/JPS5415650B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP50147533A 1974-12-20 1975-12-12 Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu Granted JPS5184530A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/534,605 US3961251A (en) 1974-12-20 1974-12-20 Testing embedded arrays
US05/534,608 US3961254A (en) 1974-12-20 1974-12-20 Testing embedded arrays

Publications (2)

Publication Number Publication Date
JPS5184530A true JPS5184530A (en) 1976-07-23
JPS5415650B2 JPS5415650B2 (en) 1979-06-16

Family

ID=27064528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50147533A Granted JPS5184530A (en) 1974-12-20 1975-12-12 Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu

Country Status (2)

Country Link
JP (1) JPS5184530A (en)
GB (1) GB1525009A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525109A (en) * 1978-08-09 1980-02-22 Fujitsu Ltd Logic circuit
JPS5614357A (en) * 1979-07-16 1981-02-12 Matsushita Electric Ind Co Ltd Diagnostic control unit

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59185097A (en) * 1983-04-04 1984-10-20 Oki Electric Ind Co Ltd Memory device with self-diagnostic function

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE CONFEREMCE RECORD ON SWITCHING CIRCUIT THEORY AND LOGICAL DESIGN=1965US *
IEEE CONFERENCE RECORD ON SWITCHING CIRCUIT THEORY AND LOGICAL DESIGN=1965US *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5525109A (en) * 1978-08-09 1980-02-22 Fujitsu Ltd Logic circuit
JPS5614357A (en) * 1979-07-16 1981-02-12 Matsushita Electric Ind Co Ltd Diagnostic control unit

Also Published As

Publication number Publication date
GB1525009A (en) 1978-09-20
JPS5415650B2 (en) 1979-06-16

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