JPS52116101A - Packet multiplication unit - Google Patents

Packet multiplication unit

Info

Publication number
JPS52116101A
JPS52116101A JP3266576A JP3266576A JPS52116101A JP S52116101 A JPS52116101 A JP S52116101A JP 3266576 A JP3266576 A JP 3266576A JP 3266576 A JP3266576 A JP 3266576A JP S52116101 A JPS52116101 A JP S52116101A
Authority
JP
Japan
Prior art keywords
multiplication unit
packet multiplication
packet
data
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3266576A
Other languages
Japanese (ja)
Inventor
Takeshi Hyodo
Minoru Sugano
Yuzo Maeda
Makoto Shinooka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
NTT Inc
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP3266576A priority Critical patent/JPS52116101A/en
Publication of JPS52116101A publication Critical patent/JPS52116101A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer And Data Communications (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To perform address designation for the buffer corresponding to data terminal with reduced load of processing section by adding store register and address conversion circuit, and thus to realize high-speed operation of data.
JP3266576A 1976-03-26 1976-03-26 Packet multiplication unit Pending JPS52116101A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3266576A JPS52116101A (en) 1976-03-26 1976-03-26 Packet multiplication unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3266576A JPS52116101A (en) 1976-03-26 1976-03-26 Packet multiplication unit

Publications (1)

Publication Number Publication Date
JPS52116101A true JPS52116101A (en) 1977-09-29

Family

ID=12365152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3266576A Pending JPS52116101A (en) 1976-03-26 1976-03-26 Packet multiplication unit

Country Status (1)

Country Link
JP (1) JPS52116101A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501436A (en) * 1982-08-13 1984-08-09 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Multiplexed first-in first-out queue
JPS61163754A (en) * 1985-01-14 1986-07-24 Nec Corp Data transmitting and receiving system using plural loops
JPH04137157A (en) * 1990-09-28 1992-05-12 Nec Corp Data transfer device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501436A (en) * 1982-08-13 1984-08-09 ウエスタ−ン　エレクトリツク　カムパニ−，インコ−ポレ−テツド Multiplexed first-in first-out queue
JPS61163754A (en) * 1985-01-14 1986-07-24 Nec Corp Data transmitting and receiving system using plural loops
JPH04137157A (en) * 1990-09-28 1992-05-12 Nec Corp Data transfer device

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