JPS52119002A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS52119002A
JPS52119002A JP3528676A JP3528676A JPS52119002A JP S52119002 A JPS52119002 A JP S52119002A JP 3528676 A JP3528676 A JP 3528676A JP 3528676 A JP3528676 A JP 3528676A JP S52119002 A JPS52119002 A JP S52119002A
Authority
JP
Japan
Prior art keywords
signal processing
processing circuit
output signal
forming
automatic control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3528676A
Other languages
Japanese (ja)
Inventor
Takahisa Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3528676A priority Critical patent/JPS52119002A/en
Publication of JPS52119002A publication Critical patent/JPS52119002A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0332—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with an integrator-detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To obtain simultaneously the clock pulse and the regenerative output signal corrected synchronously by forming the high efficient automatic control loop.
JP3528676A 1976-03-31 1976-03-31 Signal processing circuit Pending JPS52119002A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3528676A JPS52119002A (en) 1976-03-31 1976-03-31 Signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3528676A JPS52119002A (en) 1976-03-31 1976-03-31 Signal processing circuit

Publications (1)

Publication Number Publication Date
JPS52119002A true JPS52119002A (en) 1977-10-06

Family

ID=12437518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3528676A Pending JPS52119002A (en) 1976-03-31 1976-03-31 Signal processing circuit

Country Status (1)

Country Link
JP (1) JPS52119002A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156922A (en) * 1984-12-21 1986-07-16 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Replication of clock signal from manchester's coded signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61156922A (en) * 1984-12-21 1986-07-16 アドバンスト・マイクロ・デイバイシズ・インコーポレーテツド Replication of clock signal from manchester's coded signal

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