JPS52149446A - Coupling system between a plural number of cpu#s and one memory unit - Google Patents

Coupling system between a plural number of cpu#s and one memory unit

Info

Publication number
JPS52149446A
JPS52149446A JP6674276A JP6674276A JPS52149446A JP S52149446 A JPS52149446 A JP S52149446A JP 6674276 A JP6674276 A JP 6674276A JP 6674276 A JP6674276 A JP 6674276A JP S52149446 A JPS52149446 A JP S52149446A
Authority
JP
Japan
Prior art keywords
cpu
memory unit
plural number
coupling system
accessed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6674276A
Other languages
Japanese (ja)
Inventor
Masayuki Tsutsumi
Tsutomu Matsumoto
Masazumi Ishibashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Signal Co Ltd
Original Assignee
Nippon Signal Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Signal Co Ltd filed Critical Nippon Signal Co Ltd
Priority to JP6674276A priority Critical patent/JPS52149446A/en
Publication of JPS52149446A publication Critical patent/JPS52149446A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To realize the coupling system to perform the most smooth process control according to the priority of the processing level, when one memory unit commonly used by a plural number of dispersed CPU's is accessed.
COPYRIGHT: (C)1977,JPO&Japio
JP6674276A 1976-06-08 1976-06-08 Coupling system between a plural number of cpu#s and one memory unit Pending JPS52149446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6674276A JPS52149446A (en) 1976-06-08 1976-06-08 Coupling system between a plural number of cpu#s and one memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6674276A JPS52149446A (en) 1976-06-08 1976-06-08 Coupling system between a plural number of cpu#s and one memory unit

Publications (1)

Publication Number Publication Date
JPS52149446A true JPS52149446A (en) 1977-12-12

Family

ID=13324623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6674276A Pending JPS52149446A (en) 1976-06-08 1976-06-08 Coupling system between a plural number of cpu#s and one memory unit

Country Status (1)

Country Link
JP (1) JPS52149446A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965369A (en) * 1982-09-03 1984-04-13 セコイア・システムス・インコ−ポレ−テツド Computer system
JPS60252982A (en) * 1984-05-30 1985-12-13 Serbo Rand Kk Method of memory access in computer system having multi-cpu

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061955A (en) * 1973-09-29 1975-05-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061955A (en) * 1973-09-29 1975-05-27

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5965369A (en) * 1982-09-03 1984-04-13 セコイア・システムス・インコ−ポレ−テツド Computer system
JPS60252982A (en) * 1984-05-30 1985-12-13 Serbo Rand Kk Method of memory access in computer system having multi-cpu

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