JPS52152153A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS52152153A
JPS52152153A JP6881576A JP6881576A JPS52152153A JP S52152153 A JPS52152153 A JP S52152153A JP 6881576 A JP6881576 A JP 6881576A JP 6881576 A JP6881576 A JP 6881576A JP S52152153 A JPS52152153 A JP S52152153A
Authority
JP
Japan
Prior art keywords
logical circuit
noise
delay time
output circuit
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6881576A
Other languages
Japanese (ja)
Inventor
Goro Kitsukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6881576A priority Critical patent/JPS52152153A/en
Publication of JPS52152153A publication Critical patent/JPS52152153A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/086—Emitter coupled logic
    • H03K19/0866—Stacked emitter coupled logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent increment of the delay time of the output circuit owing to the noise which is generated in LSI, specially in the reference voltage, at the switching time of the memory output, and to reduce the delay time of the output circuit by using this noise reversely.
JP6881576A 1976-06-14 1976-06-14 Logical circuit Pending JPS52152153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6881576A JPS52152153A (en) 1976-06-14 1976-06-14 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6881576A JPS52152153A (en) 1976-06-14 1976-06-14 Logical circuit

Publications (1)

Publication Number Publication Date
JPS52152153A true JPS52152153A (en) 1977-12-17

Family

ID=13384580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6881576A Pending JPS52152153A (en) 1976-06-14 1976-06-14 Logical circuit

Country Status (1)

Country Link
JP (1) JPS52152153A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195322A (en) * 1982-05-10 1983-11-14 Matsushita Electric Ind Co Ltd Field effect transistor circuit
JPS61260710A (en) * 1985-05-14 1986-11-18 Sony Corp Flip-flop

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58195322A (en) * 1982-05-10 1983-11-14 Matsushita Electric Ind Co Ltd Field effect transistor circuit
JPS61260710A (en) * 1985-05-14 1986-11-18 Sony Corp Flip-flop

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