JPS522207A - Receiving circuit - Google Patents

Receiving circuit

Info

Publication number
JPS522207A
JPS522207A JP50076690A JP7669075A JPS522207A JP S522207 A JPS522207 A JP S522207A JP 50076690 A JP50076690 A JP 50076690A JP 7669075 A JP7669075 A JP 7669075A JP S522207 A JPS522207 A JP S522207A
Authority
JP
Japan
Prior art keywords
receiving circuit
extract
data transmission
receiving signals
demodulation means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50076690A
Other languages
Japanese (ja)
Inventor
Yoshiyuki Yugawa
Toshiharu Ogasawara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50076690A priority Critical patent/JPS522207A/en
Publication of JPS522207A publication Critical patent/JPS522207A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To extract a synchronous signal adapted to perform synchronous data transmission from receiving signals by utilizing start-stop synchronizing modulation and demodulation means.
JP50076690A 1975-06-24 1975-06-24 Receiving circuit Pending JPS522207A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50076690A JPS522207A (en) 1975-06-24 1975-06-24 Receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50076690A JPS522207A (en) 1975-06-24 1975-06-24 Receiving circuit

Publications (1)

Publication Number Publication Date
JPS522207A true JPS522207A (en) 1977-01-08

Family

ID=13612448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50076690A Pending JPS522207A (en) 1975-06-24 1975-06-24 Receiving circuit

Country Status (1)

Country Link
JP (1) JPS522207A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03217513A (en) * 1990-01-19 1991-09-25 Hiroshige Uchida Vertical drain method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03217513A (en) * 1990-01-19 1991-09-25 Hiroshige Uchida Vertical drain method

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