JPS5240034A - Memory control equipment - Google Patents

Memory control equipment

Info

Publication number
JPS5240034A
JPS5240034A JP50115646A JP11564675A JPS5240034A JP S5240034 A JPS5240034 A JP S5240034A JP 50115646 A JP50115646 A JP 50115646A JP 11564675 A JP11564675 A JP 11564675A JP S5240034 A JPS5240034 A JP S5240034A
Authority
JP
Japan
Prior art keywords
control equipment
memory control
refreshoperation
lowering
secure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50115646A
Other languages
Japanese (ja)
Inventor
Yoshio Inui
Osamu Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP50115646A priority Critical patent/JPS5240034A/en
Publication of JPS5240034A publication Critical patent/JPS5240034A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To secure a information processing system, which is capable of refreshoperation of memory unit without lowering the processing capability of the central processing equipment.
JP50115646A 1975-09-26 1975-09-26 Memory control equipment Pending JPS5240034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50115646A JPS5240034A (en) 1975-09-26 1975-09-26 Memory control equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50115646A JPS5240034A (en) 1975-09-26 1975-09-26 Memory control equipment

Publications (1)

Publication Number Publication Date
JPS5240034A true JPS5240034A (en) 1977-03-28

Family

ID=14667782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50115646A Pending JPS5240034A (en) 1975-09-26 1975-09-26 Memory control equipment

Country Status (1)

Country Link
JP (1) JPS5240034A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061957A (en) * 1973-09-28 1975-05-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5061957A (en) * 1973-09-28 1975-05-27

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