JPS5240972A - Packaging construction of semiconductor device - Google Patents

Packaging construction of semiconductor device

Info

Publication number
JPS5240972A
JPS5240972A JP50116587A JP11658775A JPS5240972A JP S5240972 A JPS5240972 A JP S5240972A JP 50116587 A JP50116587 A JP 50116587A JP 11658775 A JP11658775 A JP 11658775A JP S5240972 A JPS5240972 A JP S5240972A
Authority
JP
Japan
Prior art keywords
semiconductor device
packaging construction
conduct
paste
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50116587A
Other languages
Japanese (ja)
Inventor
Yuzo Maekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP50116587A priority Critical patent/JPS5240972A/en
Publication of JPS5240972A publication Critical patent/JPS5240972A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To conduct IC electrode to leads by means of a paste-form conductive material via the through-hole of IC lead pattern formed on an insulating substrate, thereby forming inexpensive and highly reliable wireless bonding.
COPYRIGHT: (C)1977,JPO&Japio
JP50116587A 1975-09-26 1975-09-26 Packaging construction of semiconductor device Pending JPS5240972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50116587A JPS5240972A (en) 1975-09-26 1975-09-26 Packaging construction of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50116587A JPS5240972A (en) 1975-09-26 1975-09-26 Packaging construction of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5240972A true JPS5240972A (en) 1977-03-30

Family

ID=14690817

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50116587A Pending JPS5240972A (en) 1975-09-26 1975-09-26 Packaging construction of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5240972A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955132A (en) * 1987-11-16 1990-09-11 Sharp Kabushiki Kaisha Method for mounting a semiconductor chip
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
WO1998048455A1 (en) * 1997-04-21 1998-10-29 Seiko Epson Corporation Interelectrode connecting structure, interelectrode connecting method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4955132A (en) * 1987-11-16 1990-09-11 Sharp Kabushiki Kaisha Method for mounting a semiconductor chip
US5452182A (en) * 1990-04-05 1995-09-19 Martin Marietta Corporation Flexible high density interconnect structure and flexibly interconnected system
WO1998048455A1 (en) * 1997-04-21 1998-10-29 Seiko Epson Corporation Interelectrode connecting structure, interelectrode connecting method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic equipment
US6357111B1 (en) 1997-04-21 2002-03-19 Seiko Epson Corporation Inter-electrode connection structure, inter-electrode connection method, semiconductor device, semiconductor mounting method, liquid crystal device, and electronic apparatus

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