JPS5253601A - Stereo demodulation circuit - Google Patents

Stereo demodulation circuit

Info

Publication number
JPS5253601A
JPS5253601A JP12964475A JP12964475A JPS5253601A JP S5253601 A JPS5253601 A JP S5253601A JP 12964475 A JP12964475 A JP 12964475A JP 12964475 A JP12964475 A JP 12964475A JP S5253601 A JPS5253601 A JP S5253601A
Authority
JP
Japan
Prior art keywords
demodulation circuit
circuit
stereo demodulation
current
thedelete
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12964475A
Other languages
Japanese (ja)
Other versions
JPS587096B2 (en
Inventor
Mitsuo Osawa
Tadatoshi Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP12964475A priority Critical patent/JPS587096B2/en
Publication of JPS5253601A publication Critical patent/JPS5253601A/en
Publication of JPS587096B2 publication Critical patent/JPS587096B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D1/00—Demodulation of amplitude-modulated oscillations
    • H03D1/22—Homodyne or synchrodyne circuits
    • H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
    • H03D1/2227—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using switches for the decoding

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stereo-Broadcasting Methods (AREA)

Abstract

PURPOSE:The DC current of identical value is supplied to double differential amplifier trnasistor from current supply circuit in order to increase demodualtion circuit gain, restrain high frequency distortion occurrence, and thedelete ripple effect of power source voltage. Thus, the circuit constitution can be simplified.
JP12964475A 1975-10-28 1975-10-28 stereo fukuchiyou warmer Expired JPS587096B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12964475A JPS587096B2 (en) 1975-10-28 1975-10-28 stereo fukuchiyou warmer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12964475A JPS587096B2 (en) 1975-10-28 1975-10-28 stereo fukuchiyou warmer

Publications (2)

Publication Number Publication Date
JPS5253601A true JPS5253601A (en) 1977-04-30
JPS587096B2 JPS587096B2 (en) 1983-02-08

Family

ID=15014599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12964475A Expired JPS587096B2 (en) 1975-10-28 1975-10-28 stereo fukuchiyou warmer

Country Status (1)

Country Link
JP (1) JPS587096B2 (en)

Also Published As

Publication number Publication date
JPS587096B2 (en) 1983-02-08

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