JPS531427A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS531427A
JPS531427A JP7557676A JP7557676A JPS531427A JP S531427 A JPS531427 A JP S531427A JP 7557676 A JP7557676 A JP 7557676A JP 7557676 A JP7557676 A JP 7557676A JP S531427 A JPS531427 A JP S531427A
Authority
JP
Japan
Prior art keywords
control system
memory control
start pulse
memory
thru
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7557676A
Other languages
Japanese (ja)
Other versions
JPS5920192B2 (en
Inventor
Yoshio Nakano
Hitoshi Sato
Tadashi Kawanobe
Noboru Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NTT Inc
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7557676A priority Critical patent/JPS5920192B2/en
Publication of JPS531427A publication Critical patent/JPS531427A/en
Publication of JPS5920192B2 publication Critical patent/JPS5920192B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To enable the reception of the memory response signal by using the common bus, thru the use of the start pulse of different width and the control of the start pulse width, in simultaneous start of a plural number of memory units.
JP7557676A 1976-06-28 1976-06-28 Memory control method Expired JPS5920192B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7557676A JPS5920192B2 (en) 1976-06-28 1976-06-28 Memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7557676A JPS5920192B2 (en) 1976-06-28 1976-06-28 Memory control method

Publications (2)

Publication Number Publication Date
JPS531427A true JPS531427A (en) 1978-01-09
JPS5920192B2 JPS5920192B2 (en) 1984-05-11

Family

ID=13580144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7557676A Expired JPS5920192B2 (en) 1976-06-28 1976-06-28 Memory control method

Country Status (1)

Country Link
JP (1) JPS5920192B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5985988U (en) * 1982-12-01 1984-06-11 富士写真光機株式会社 Vibration isolator for interference measuring instruments

Also Published As

Publication number Publication date
JPS5920192B2 (en) 1984-05-11

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