JPS5358731A - Memory address extension method - Google Patents
Memory address extension methodInfo
- Publication number
- JPS5358731A JPS5358731A JP13397076A JP13397076A JPS5358731A JP S5358731 A JPS5358731 A JP S5358731A JP 13397076 A JP13397076 A JP 13397076A JP 13397076 A JP13397076 A JP 13397076A JP S5358731 A JPS5358731 A JP S5358731A
- Authority
- JP
- Japan
- Prior art keywords
- memory address
- extension method
- address extension
- main memory
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bus Control (AREA)
- Memory System (AREA)
Abstract
PURPOSE:To secure an access for a main memory in which CPU and low-speed input/output unit are extended, by part of the channel control ward region within the main memory to utilize it as a memory address region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13397076A JPS5358731A (en) | 1976-11-08 | 1976-11-08 | Memory address extension method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13397076A JPS5358731A (en) | 1976-11-08 | 1976-11-08 | Memory address extension method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5358731A true JPS5358731A (en) | 1978-05-26 |
Family
ID=15117325
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13397076A Pending JPS5358731A (en) | 1976-11-08 | 1976-11-08 | Memory address extension method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5358731A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55157027A (en) * | 1979-05-25 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Input and output transfer control unit |
| JPS58146951A (en) * | 1982-02-26 | 1983-09-01 | Ricoh Co Ltd | Address extension method |
| JPS58225422A (en) * | 1982-06-25 | 1983-12-27 | Toshiba Corp | Data controller |
| JPS5981724A (en) * | 1982-11-02 | 1984-05-11 | Hitachi Electronics Eng Co Ltd | Expanding method for address space of dma controller |
| JPS59206925A (en) * | 1983-05-10 | 1984-11-22 | Panafacom Ltd | Data processing system |
| JPS6029862A (en) * | 1983-07-28 | 1985-02-15 | Tokyo Electric Co Ltd | Designating device for high order address bit of dma |
| JPS6072052A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Memory access system |
-
1976
- 1976-11-08 JP JP13397076A patent/JPS5358731A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55157027A (en) * | 1979-05-25 | 1980-12-06 | Matsushita Electric Ind Co Ltd | Input and output transfer control unit |
| JPS58146951A (en) * | 1982-02-26 | 1983-09-01 | Ricoh Co Ltd | Address extension method |
| JPS58225422A (en) * | 1982-06-25 | 1983-12-27 | Toshiba Corp | Data controller |
| JPS5981724A (en) * | 1982-11-02 | 1984-05-11 | Hitachi Electronics Eng Co Ltd | Expanding method for address space of dma controller |
| JPS59206925A (en) * | 1983-05-10 | 1984-11-22 | Panafacom Ltd | Data processing system |
| JPS6029862A (en) * | 1983-07-28 | 1985-02-15 | Tokyo Electric Co Ltd | Designating device for high order address bit of dma |
| JPS6072052A (en) * | 1983-09-29 | 1985-04-24 | Nec Corp | Memory access system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS52103921A (en) | Data processing unit | |
| JPS5334429A (en) | Memory control system | |
| JPS5441631A (en) | Fixed program set system for control | |
| JPS5363935A (en) | Memory address control system | |
| JPS5335437A (en) | Data processing unit having address converting functions | |
| JPS543441A (en) | High-speed arithmetic system | |
| JPS5362946A (en) | Data processor | |
| JPS52146527A (en) | Computer | |
| JPS5330838A (en) | Erasing method of erasable rom | |
| JPS53121426A (en) | Data processor having address conversion unit | |
| JPS52155937A (en) | Data transfer unit | |
| JPS5384631A (en) | Address assigning system of memory unit | |
| JPS52139886A (en) | Sequence controller | |
| JPS5391637A (en) | Data processor | |
| JPS53121435A (en) | Arithmetic operation control unit | |
| JPS52130209A (en) | Data alteration system | |
| JPS5335436A (en) | Data processing unit having address converting functions | |
| JPS5420626A (en) | Memory circuit | |
| JPS5352329A (en) | Electronic computer | |
| JPS5258433A (en) | Subchannel control system | |
| JPS5225538A (en) | Input control system of control use data | |
| JPS53108241A (en) | Memory address modification system | |
| JPS544027A (en) | Memory readout unit | |
| JPS52112237A (en) | Memory control unit | |
| JPS51122349A (en) | Jump address determination method by external input |