JPS5368573A - Hermetic sealing method of semiconductor device - Google Patents

Hermetic sealing method of semiconductor device

Info

Publication number
JPS5368573A
JPS5368573A JP14430976A JP14430976A JPS5368573A JP S5368573 A JPS5368573 A JP S5368573A JP 14430976 A JP14430976 A JP 14430976A JP 14430976 A JP14430976 A JP 14430976A JP S5368573 A JPS5368573 A JP S5368573A
Authority
JP
Japan
Prior art keywords
semiconductor device
chip
sealing method
hermetic sealing
lead conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14430976A
Other languages
Japanese (ja)
Inventor
Hiroharu Niinobu
Toshio Sogo
Toru Kameda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP14430976A priority Critical patent/JPS5368573A/en
Publication of JPS5368573A publication Critical patent/JPS5368573A/en
Pending legal-status Critical Current

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261—Processes for packaging MEMS devices
    • B81C1/00269—Bonding of solid lids or wafers to the substrate

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE: To save high temperature treatment processes at least once by bonding a semiconductor chip to a lead conductor which is integrated in the form of a lead frame, connecting each electrode of the chip to each lead conductor by fine metal wires, thereafter sealing the chip in a ceramic base and a ceramic cap by using low melting point bonding glass.
COPYRIGHT: (C)1978,JPO&Japio
JP14430976A 1976-11-30 1976-11-30 Hermetic sealing method of semiconductor device Pending JPS5368573A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14430976A JPS5368573A (en) 1976-11-30 1976-11-30 Hermetic sealing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14430976A JPS5368573A (en) 1976-11-30 1976-11-30 Hermetic sealing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5368573A true JPS5368573A (en) 1978-06-19

Family

ID=15359077

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14430976A Pending JPS5368573A (en) 1976-11-30 1976-11-30 Hermetic sealing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5368573A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599747A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Package for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5599747A (en) * 1979-01-26 1980-07-30 Hitachi Ltd Package for semiconductor device

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