JPS5376719A - Output buffer circuit with tri-state control - Google Patents

Output buffer circuit with tri-state control

Info

Publication number
JPS5376719A
JPS5376719A JP15303676A JP15303676A JPS5376719A JP S5376719 A JPS5376719 A JP S5376719A JP 15303676 A JP15303676 A JP 15303676A JP 15303676 A JP15303676 A JP 15303676A JP S5376719 A JPS5376719 A JP S5376719A
Authority
JP
Japan
Prior art keywords
tri
output buffer
buffer circuit
state control
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15303676A
Other languages
Japanese (ja)
Inventor
Ryusuke Hoshikawa
Hideo Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15303676A priority Critical patent/JPS5376719A/en
Publication of JPS5376719A publication Critical patent/JPS5376719A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:A logical circuit is controlled by connecting three parallel MOS transistors in series and by using a control signal so as to reduce the nubmer of MOS transistors which drive in series with a data input, thereby making the input capacity small.
JP15303676A 1976-12-20 1976-12-20 Output buffer circuit with tri-state control Pending JPS5376719A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15303676A JPS5376719A (en) 1976-12-20 1976-12-20 Output buffer circuit with tri-state control

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15303676A JPS5376719A (en) 1976-12-20 1976-12-20 Output buffer circuit with tri-state control

Publications (1)

Publication Number Publication Date
JPS5376719A true JPS5376719A (en) 1978-07-07

Family

ID=15553562

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15303676A Pending JPS5376719A (en) 1976-12-20 1976-12-20 Output buffer circuit with tri-state control

Country Status (1)

Country Link
JP (1) JPS5376719A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1980001124A1 (en) * 1978-11-17 1980-05-29 Fujitsu Ltd Amplifier circuit
JPS55141826A (en) * 1979-04-24 1980-11-06 Seiko Epson Corp Input circuit for integrated circuit
JPS606346U (en) * 1983-06-27 1985-01-17 セイコーインスツルメンツ株式会社 signal delay circuit
JPS61173519A (en) * 1985-01-28 1986-08-05 Sharp Corp Tri-state circuit
US4725982A (en) * 1985-03-29 1988-02-16 Kabushiki Kaisha Toshiba Tri-state buffer circuit
JPH04249917A (en) * 1991-01-08 1992-09-04 Nec Ic Microcomput Syst Ltd Three-state output buffer

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1980001124A1 (en) * 1978-11-17 1980-05-29 Fujitsu Ltd Amplifier circuit
JPS55141826A (en) * 1979-04-24 1980-11-06 Seiko Epson Corp Input circuit for integrated circuit
JPS606346U (en) * 1983-06-27 1985-01-17 セイコーインスツルメンツ株式会社 signal delay circuit
JPS61173519A (en) * 1985-01-28 1986-08-05 Sharp Corp Tri-state circuit
US4725982A (en) * 1985-03-29 1988-02-16 Kabushiki Kaisha Toshiba Tri-state buffer circuit
JPH04249917A (en) * 1991-01-08 1992-09-04 Nec Ic Microcomput Syst Ltd Three-state output buffer

Similar Documents

Publication Publication Date Title
JPS6418312A (en) Four-state input/output control circuit
JPS5376719A (en) Output buffer circuit with tri-state control
JPS5373954A (en) Divider circuit
JPS55141825A (en) Cmos output circuit
JPS54154964A (en) Programable counter
JPS6460015A (en) Flip flop circuit
JPS533049A (en) Logical circuit
JPS52140241A (en) Binary #-digit addition circuit
JPS5684034A (en) Logic circuit
JPS5368047A (en) Input signal buffer circuit
JPS53118959A (en) Non-volatile flip flop circuit
JPS52144954A (en) Inverter circuit
JPS52116129A (en) Logical circuit
JPS5379339A (en) Basic circuit of progammable cmos logical array
JPS5531357A (en) Insulated gate type field effect transistor logic gate circuit
JPS52125244A (en) Memory circuit
JPS5355950A (en) Logical gate circuit
JPS5672533A (en) Latch circuit
JPS536557A (en) Logic circuit
JPS5373951A (en) Flip-flop circuit
JPS5432258A (en) Exclusive logical sum circuit
JPS5352348A (en) Cmos input circuit
JPS5471959A (en) Array logical operation circuit
JPS5429531A (en) Sense circuit for cmos static random access memory
JPS5335360A (en) Semiconductor logical circuit