JPS54101631A - Bus control system - Google Patents

Bus control system

Info

Publication number
JPS54101631A
JPS54101631A JP854978A JP854978A JPS54101631A JP S54101631 A JPS54101631 A JP S54101631A JP 854978 A JP854978 A JP 854978A JP 854978 A JP854978 A JP 854978A JP S54101631 A JPS54101631 A JP S54101631A
Authority
JP
Japan
Prior art keywords
request
bus
signal line
output
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP854978A
Other languages
Japanese (ja)
Inventor
Nobuteru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP854978A priority Critical patent/JPS54101631A/en
Publication of JPS54101631A publication Critical patent/JPS54101631A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To improve a bus use efficiency by providing the constitution where the bus cycle is repeated at a fixed-time interval by using the request device waiting request signal of connected devices in respect to the control system of the common bus connecting a number of processing devices and I/O control devices, etc.
CONSTITUTION: The control circuit connected to common busses 1 to 9 is provided, and within this circuit, user request FF 10 which is set by set pulse 101 generated when each device uses a bus and is held until data transfer is completed and bus request FF 20 which is set by the output of this FF 10 are provided and indicated on use request signal line 7. Further, bus assignment circuit 18 which outputs output 181 when request data effective signal line 4 and requested device response signal line 5 are 0 and output 201 of FF 20 is 1 and the signal from bus use assignment signal line 8 does not request the bus use is provided, and effective FF 30 is set by this output. Then, when the request waiting signal from the requested device is sent, FF 20 is reset to stop the transmission of request signals.
COPYRIGHT: (C)1979,JPO&Japio
JP854978A 1978-01-27 1978-01-27 Bus control system Pending JPS54101631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP854978A JPS54101631A (en) 1978-01-27 1978-01-27 Bus control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP854978A JPS54101631A (en) 1978-01-27 1978-01-27 Bus control system

Publications (1)

Publication Number Publication Date
JPS54101631A true JPS54101631A (en) 1979-08-10

Family

ID=11696207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP854978A Pending JPS54101631A (en) 1978-01-27 1978-01-27 Bus control system

Country Status (1)

Country Link
JP (1) JPS54101631A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882327A (en) * 1981-11-11 1983-05-17 Mitsubishi Electric Corp Bus controller
JPS6077254A (en) * 1983-10-04 1985-05-01 Fujitsu Ltd Control system of common bus

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882327A (en) * 1981-11-11 1983-05-17 Mitsubishi Electric Corp Bus controller
JPS6077254A (en) * 1983-10-04 1985-05-01 Fujitsu Ltd Control system of common bus

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