JPS54107635A - Program unit - Google Patents

Program unit

Info

Publication number
JPS54107635A
JPS54107635A JP1446578A JP1446578A JPS54107635A JP S54107635 A JPS54107635 A JP S54107635A JP 1446578 A JP1446578 A JP 1446578A JP 1446578 A JP1446578 A JP 1446578A JP S54107635 A JPS54107635 A JP S54107635A
Authority
JP
Japan
Prior art keywords
ram
constitution
input
bit
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1446578A
Other languages
Japanese (ja)
Inventor
Osamu Akiba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP1446578A priority Critical patent/JPS54107635A/en
Publication of JPS54107635A publication Critical patent/JPS54107635A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store

Abstract

PURPOSE:To perform write-in only to a given bit in one word, by connecting the RAM of one bit constitution on the one address line, making the input line in common connection, and performing write-in with the external switch placed at the input terminal. CONSTITUTION:The RAM's 1 to 4 in one bit constitution are used like ROM changeable, the operation of system is written in RAM and the data are picked up and used for control. RAM's 1 to 4 are connected on the one address line 5. Further, the input line 6 of RAM's 1 to 4 is in common connection, and the chip selection input terminal CS of RAM's 1 to 4 is provided with a plurality of external switches SW1 to SW4. The switches select RAM 1 to 4 and input is made through RAM selected.
JP1446578A 1978-02-10 1978-02-10 Program unit Pending JPS54107635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1446578A JPS54107635A (en) 1978-02-10 1978-02-10 Program unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1446578A JPS54107635A (en) 1978-02-10 1978-02-10 Program unit

Publications (1)

Publication Number Publication Date
JPS54107635A true JPS54107635A (en) 1979-08-23

Family

ID=11861796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1446578A Pending JPS54107635A (en) 1978-02-10 1978-02-10 Program unit

Country Status (1)

Country Link
JP (1) JPS54107635A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4956541A (en) * 1972-09-30 1974-06-01
JPS5178645A (en) * 1974-12-28 1976-07-08 Nippon Electric Co

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4956541A (en) * 1972-09-30 1974-06-01
JPS5178645A (en) * 1974-12-28 1976-07-08 Nippon Electric Co

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