JPS54110773A - Parallel signal process system for hadamard conversion system - Google Patents

Parallel signal process system for hadamard conversion system

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Publication number
JPS54110773A
JPS54110773A JP1738678A JP1738678A JPS54110773A JP S54110773 A JPS54110773 A JP S54110773A JP 1738678 A JP1738678 A JP 1738678A JP 1738678 A JP1738678 A JP 1738678A JP S54110773 A JPS54110773 A JP S54110773A
Authority
JP
Japan
Prior art keywords
signal
piled
clock signal
parallel
parallel signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1738678A
Other languages
Japanese (ja)
Other versions
JPS6046867B2 (en
Inventor
Atsushi Matsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP1738678A priority Critical patent/JPS6046867B2/en
Publication of JPS54110773A publication Critical patent/JPS54110773A/en
Publication of JPS6046867B2 publication Critical patent/JPS6046867B2/en
Expired legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)

Abstract

PURPOSE: To facilitate an easy discrimination between the information signal and the clock signal by using only the optional specific signal among the parallel signals after the Hadamard reverse conversion for the parallel signal piled on with the clock signal and also giving the piling with the large output.
CONSTITUTION: Parallel signal x1 and x2 are converted via Hadamard conversion circuit 1 as shown in Eq. I to secure parallel signal as y1=a(x1+x2) and Y2= a(x1-x2) respectively. Clock signal (e) is piled on y1 and y2 through adder 31 and 32, and a conversion as shown in Eq. II is given via Hadamard reverse conversion circuit 2 to obtain the parallel signal as x1'=b(y1+y2+2e) and x2'=b(y1-y2) respectively. Thus, the clock signal is piled only onto x1' with a double size obtained. In case the clock signal is piled only onto x2', e is piled on y1 and y2 in the opposite phase. In such way, the clock signal is piled on only the potional specific signal system wit a large output, thus ensuring a simple discrimination between the information signal and the clock signal.
COPYRIGHT: (C)1979,JPO&Japio
JP1738678A 1978-02-17 1978-02-17 Parallel signal processing method in Hadamard transform system Expired JPS6046867B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1738678A JPS6046867B2 (en) 1978-02-17 1978-02-17 Parallel signal processing method in Hadamard transform system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1738678A JPS6046867B2 (en) 1978-02-17 1978-02-17 Parallel signal processing method in Hadamard transform system

Publications (2)

Publication Number Publication Date
JPS54110773A true JPS54110773A (en) 1979-08-30
JPS6046867B2 JPS6046867B2 (en) 1985-10-18

Family

ID=11942554

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1738678A Expired JPS6046867B2 (en) 1978-02-17 1978-02-17 Parallel signal processing method in Hadamard transform system

Country Status (1)

Country Link
JP (1) JPS6046867B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137145U (en) * 1988-03-14 1989-09-20

Also Published As

Publication number Publication date
JPS6046867B2 (en) 1985-10-18

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