JPS54121012A - Reception reproducing circuit for data transmission system - Google Patents
Reception reproducing circuit for data transmission systemInfo
- Publication number
- JPS54121012A JPS54121012A JP2773778A JP2773778A JPS54121012A JP S54121012 A JPS54121012 A JP S54121012A JP 2773778 A JP2773778 A JP 2773778A JP 2773778 A JP2773778 A JP 2773778A JP S54121012 A JPS54121012 A JP S54121012A
- Authority
- JP
- Japan
- Prior art keywords
- output
- noise
- comparator
- data transmission
- transmission system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 title 1
- 230000037430 deletion Effects 0.000 abstract 1
- 238000012217 deletion Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
- H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To ensure an assured deletion even of such common mode noise that exceeds the reference level of the comparator. CONSTITUTION:Output V01 and V02 of comparator 6 and 7 are led to exclusive logic sum circuit 9, and output V0 of exclusive logic sum circuit 9 is used as the reception reproduction output. In such constitution, comparator 6 and 7 respond to the noise exceeding reference level VF when the common mode noise is supplied to 6 and 7, and the noise pulses emerge in the from of output V01 and V02. However, no noise pulse emerges at output V0 since the exclusive logic sum is secured at circuit 9 for the output of comparator 6 and 7. Accordingly, no noise reproduction is carried out.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2773778A JPS54121012A (en) | 1978-03-13 | 1978-03-13 | Reception reproducing circuit for data transmission system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2773778A JPS54121012A (en) | 1978-03-13 | 1978-03-13 | Reception reproducing circuit for data transmission system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54121012A true JPS54121012A (en) | 1979-09-19 |
Family
ID=12229334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2773778A Pending JPS54121012A (en) | 1978-03-13 | 1978-03-13 | Reception reproducing circuit for data transmission system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54121012A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020010086A (en) * | 2018-07-03 | 2020-01-16 | ローム株式会社 | Signal transmission device |
-
1978
- 1978-03-13 JP JP2773778A patent/JPS54121012A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020010086A (en) * | 2018-07-03 | 2020-01-16 | ローム株式会社 | Signal transmission device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| FI852711A0 (en) | DEAKTIVERING AV MICROORGANISM PAO ETT OSCILLERANDE MAGNETFAELT. | |
| DE3777371D1 (en) | GENERATION OF HALFTONE REPRODUCTIONS. | |
| FI840521A0 (en) | SAETT ATT AVVATTNA EN KAKA AV BIOMASS | |
| FI840082A0 (en) | COCCIDIOSLAEKEMEDEL | |
| ATE40026T1 (en) | LOSS CORRECTION CIRCUIT FOR CORRECTING VIDEO SIGNALS DISTURBED BY LOSSES. | |
| FI842262L (en) | ANORDNING VID EN MOTORSAOG FOER UPPSPLITSNING AV BARK- OCH NAEVERSKIKT PAO TRAEDSTAMMAR. | |
| CA2024362A1 (en) | Transmitting power control circuit | |
| ATE167601T1 (en) | HYBRID ANALOG DIGITAL SIGNAL PROCESSING | |
| JPS53106109A (en) | Vedio signal transmitting circuit | |
| JPS51145256A (en) | Signal detecting circuit | |
| JPS5672714A (en) | Controller for heating apparatus | |
| JPS5376815A (en) | Magnetic recorder/reproducer | |
| EP0305343A3 (en) | A threshold comparator circuit | |
| JPS51116611A (en) | Binary threshold decision circuit system | |
| JPS5390801A (en) | Semiconductor laser switching system | |
| JPS53116137A (en) | Level display device | |
| JPS51146869A (en) | Peak tracking circuit | |
| JPS5237740A (en) | Logging system for computer system | |
| JPS5378135A (en) | Semiconductor circuit | |
| JPS5332070A (en) | Pulse integrating recorder | |
| JPS52146139A (en) | Obtaining method for 3 state output by using 2 state ttl circuit | |
| JPS5232611A (en) | Terminal system | |
| JPS5610747A (en) | Photoswitch chattering preventing system for optical data transmission system | |
| JPS5319A (en) | Information reading unit | |
| JPS51112255A (en) | Signal generator |