JPS54148362A - Wired or circuit - Google Patents

Wired or circuit

Info

Publication number
JPS54148362A
JPS54148362A JP5693578A JP5693578A JPS54148362A JP S54148362 A JPS54148362 A JP S54148362A JP 5693578 A JP5693578 A JP 5693578A JP 5693578 A JP5693578 A JP 5693578A JP S54148362 A JPS54148362 A JP S54148362A
Authority
JP
Japan
Prior art keywords
circuit
constitution
signal
output
tri
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5693578A
Other languages
Japanese (ja)
Inventor
Yoshimi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP5693578A priority Critical patent/JPS54148362A/en
Publication of JPS54148362A publication Critical patent/JPS54148362A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To simplify the circuit constitution by controlling the output end of the tri-state logic element with the strobe signal. CONSTITUTION:The output ends of tri-state logic terminal TG1 and TG2 are connected in parallel to output signal line SL. At the same time, the significant signal of the input end to element TG1 and TG2 is set to the low or high level, and the output end is set under the high-impedance state by the strobe signal applying to TG1 and TG2. Thus, the significant signal can be used at either of the high and low level, simplifying the constitution of the circuit.
JP5693578A 1978-05-12 1978-05-12 Wired or circuit Pending JPS54148362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5693578A JPS54148362A (en) 1978-05-12 1978-05-12 Wired or circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5693578A JPS54148362A (en) 1978-05-12 1978-05-12 Wired or circuit

Publications (1)

Publication Number Publication Date
JPS54148362A true JPS54148362A (en) 1979-11-20

Family

ID=13041370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5693578A Pending JPS54148362A (en) 1978-05-12 1978-05-12 Wired or circuit

Country Status (1)

Country Link
JP (1) JPS54148362A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161762A (en) * 1974-11-27 1976-05-28 Hitachi Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5161762A (en) * 1974-11-27 1976-05-28 Hitachi Ltd

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