JPS54150935A - Memory switching device - Google Patents

Memory switching device

Info

Publication number
JPS54150935A
JPS54150935A JP5974278A JP5974278A JPS54150935A JP S54150935 A JPS54150935 A JP S54150935A JP 5974278 A JP5974278 A JP 5974278A JP 5974278 A JP5974278 A JP 5974278A JP S54150935 A JPS54150935 A JP S54150935A
Authority
JP
Japan
Prior art keywords
memories
circuit
switching
memory
cpu11
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5974278A
Other languages
Japanese (ja)
Inventor
Tomiji Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP5974278A priority Critical patent/JPS54150935A/en
Publication of JPS54150935A publication Critical patent/JPS54150935A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the addition of the extension memory and thus to secure the standardization and versatility for diversification of control.
CONSTITUTION: The 1st switching circuit 12 is provided to give switching in terms of software to page memories 13a, 13b ... which are connected to CPU11, and also 2nd switching circuit 14 is provided at the output part of circuit 12 to switch the hardware-type switching to those page memories. Then main memory 15 plus plural extension memories 16a, 16b ... are connected in parallel to the output part of circuit 14, and memories 13a, 13b ... are selected via CPU11 when the data process is carried out. Based on the program, the channel switching signals are sent to circuit 14, and memory 15 or one of memories 16a, 16b ... is selected. Thus, the data writing and reading is carried out to the fixed address.
COPYRIGHT: (C)1979,JPO&Japio
JP5974278A 1978-05-19 1978-05-19 Memory switching device Pending JPS54150935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5974278A JPS54150935A (en) 1978-05-19 1978-05-19 Memory switching device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5974278A JPS54150935A (en) 1978-05-19 1978-05-19 Memory switching device

Publications (1)

Publication Number Publication Date
JPS54150935A true JPS54150935A (en) 1979-11-27

Family

ID=13121974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5974278A Pending JPS54150935A (en) 1978-05-19 1978-05-19 Memory switching device

Country Status (1)

Country Link
JP (1) JPS54150935A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501061A (en) * 1981-06-29 1983-06-30 松下電器産業株式会社 Computer with extended address function

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58501061A (en) * 1981-06-29 1983-06-30 松下電器産業株式会社 Computer with extended address function

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