JPS54158149A - Clock monitor circuit - Google Patents

Clock monitor circuit

Info

Publication number
JPS54158149A
JPS54158149A JP6694678A JP6694678A JPS54158149A JP S54158149 A JPS54158149 A JP S54158149A JP 6694678 A JP6694678 A JP 6694678A JP 6694678 A JP6694678 A JP 6694678A JP S54158149 A JPS54158149 A JP S54158149A
Authority
JP
Japan
Prior art keywords
capacitor
clock
capacitors
obtaining
monitor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6694678A
Other languages
Japanese (ja)
Inventor
Masaharu Nishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6694678A priority Critical patent/JPS54158149A/en
Publication of JPS54158149A publication Critical patent/JPS54158149A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/19—Monitoring patterns of pulse trains

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)

Abstract

PURPOSE:To secure an easy monitoring for the clock fault by obtaining the OR for the terminal voltage between the capacitors which have discharge at the high- and low-level sides of the clock respectively. CONSTITUTION:When capacitor 8a features a high level via clock input 1, capacitor 8b features a low level. And when capacitor 8a is discharged periodically, capacitor 8b is charged. While capacitor 8b is discharged periodically in a high level, capacitor 8b is charged respectively. As a result, the clock fault can be detected through variation of OR output 5 by setting the time constant to a proper value for resistances 7a and 7b as well as capacitors 8a and 8b and then obtaining the OR for the discharge terminal side between those two capacitors.
JP6694678A 1978-06-02 1978-06-02 Clock monitor circuit Pending JPS54158149A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6694678A JPS54158149A (en) 1978-06-02 1978-06-02 Clock monitor circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6694678A JPS54158149A (en) 1978-06-02 1978-06-02 Clock monitor circuit

Publications (1)

Publication Number Publication Date
JPS54158149A true JPS54158149A (en) 1979-12-13

Family

ID=13330678

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6694678A Pending JPS54158149A (en) 1978-06-02 1978-06-02 Clock monitor circuit

Country Status (1)

Country Link
JP (1) JPS54158149A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005341997A (en) * 2004-05-31 2005-12-15 Samii Kk Game machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005341997A (en) * 2004-05-31 2005-12-15 Samii Kk Game machine

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