JPS5437648A - Interface circuit - Google Patents

Interface circuit

Info

Publication number
JPS5437648A
JPS5437648A JP10368677A JP10368677A JPS5437648A JP S5437648 A JPS5437648 A JP S5437648A JP 10368677 A JP10368677 A JP 10368677A JP 10368677 A JP10368677 A JP 10368677A JP S5437648 A JPS5437648 A JP S5437648A
Authority
JP
Japan
Prior art keywords
interface circuit
circuit
transistor
constitute
utilizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10368677A
Other languages
Japanese (ja)
Inventor
Ryohei Saga
Junichi Mameta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP10368677A priority Critical patent/JPS5437648A/en
Publication of JPS5437648A publication Critical patent/JPS5437648A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H03K19/01818—Interface arrangements for integrated injection logic (I2L)

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent noise margin lowering by utilizing the transistor, which is driven by the constant current, to constitute an interface circuit connecting a TTL circuit and an I<2>L circuit and preventing the voltage drop dependent upon the current limiting resistance.
JP10368677A 1977-08-31 1977-08-31 Interface circuit Pending JPS5437648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10368677A JPS5437648A (en) 1977-08-31 1977-08-31 Interface circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10368677A JPS5437648A (en) 1977-08-31 1977-08-31 Interface circuit

Publications (1)

Publication Number Publication Date
JPS5437648A true JPS5437648A (en) 1979-03-20

Family

ID=14360651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10368677A Pending JPS5437648A (en) 1977-08-31 1977-08-31 Interface circuit

Country Status (1)

Country Link
JP (1) JPS5437648A (en)

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