JPS5443642A - Branch system for microprogram - Google Patents

Branch system for microprogram

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Publication number
JPS5443642A
JPS5443642A JP10987077A JP10987077A JPS5443642A JP S5443642 A JPS5443642 A JP S5443642A JP 10987077 A JP10987077 A JP 10987077A JP 10987077 A JP10987077 A JP 10987077A JP S5443642 A JPS5443642 A JP S5443642A
Authority
JP
Japan
Prior art keywords
micro
microprogram
signal line
register
via signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10987077A
Other languages
Japanese (ja)
Inventor
Koichi Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10987077A priority Critical patent/JPS5443642A/en
Publication of JPS5443642A publication Critical patent/JPS5443642A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To make it possible to branch a microprogram in many directions with simple constitution by attaching an adder to a device controlled by the microprogram composed of several addressed micro-words.
CONSTITUTION: By the branching method of the device controlled by the microprogram composed of several addressed micro-words, the microprogram composed of several micro-words is stored in control memory unit 1. Then, one micro-word to be executed is read out from unit 1 via signal line 10 and set to register 2, thereby using it for the operational instruction of each part. At this time, the branch-destination address part of the micro-word in register 2 is applied to one side of adder 30 via signal line 20, and binary-coded hardware-state information is to the other side of adder 30 via signal line 50; and then, its output is set to micro-word address register 4. The output of this register 4 is inputted as the address of the microword of unit 1 to be executed next via signal line 40.
COPYRIGHT: (C)1979,JPO&Japio
JP10987077A 1977-09-14 1977-09-14 Branch system for microprogram Pending JPS5443642A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10987077A JPS5443642A (en) 1977-09-14 1977-09-14 Branch system for microprogram

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10987077A JPS5443642A (en) 1977-09-14 1977-09-14 Branch system for microprogram

Publications (1)

Publication Number Publication Date
JPS5443642A true JPS5443642A (en) 1979-04-06

Family

ID=14521273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10987077A Pending JPS5443642A (en) 1977-09-14 1977-09-14 Branch system for microprogram

Country Status (1)

Country Link
JP (1) JPS5443642A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277710U (en) * 1988-12-01 1990-06-14

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277710U (en) * 1988-12-01 1990-06-14

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