JPS5444803A - Synchronization system of loop circuit - Google Patents
Synchronization system of loop circuitInfo
- Publication number
- JPS5444803A JPS5444803A JP11057877A JP11057877A JPS5444803A JP S5444803 A JPS5444803 A JP S5444803A JP 11057877 A JP11057877 A JP 11057877A JP 11057877 A JP11057877 A JP 11057877A JP S5444803 A JPS5444803 A JP S5444803A
- Authority
- JP
- Japan
- Prior art keywords
- timing
- station
- signal
- loop circuit
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/422—Synchronisation for ring networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Time-Division Multiplex Systems (AREA)
- Small-Scale Networks (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
PURPOSE:To eliminate the need of a timing adjustment in each station by enabling one station to make an automatic adjustment of timing according to the variation in line length of the circuit. CONSTITUTION:When a plural number of stations are on a loop circuit, timing regulator 20 of one station makes an automatic adjustment of timing as the line length of the loop circuit varies. Namely, phase detector 22 is supplied with signal T10 from timing generator 21 via connection line 77 and with signal T11 from receiver 27 via connection line 76. This signal T11 is the signal obained by delay signal T10 by the loop circuit of timing line 61, driver circuit 24 and receiver 27 and detector 22 detects phase difference TD between both the signals to obtain delay time TD1, which is transmitted to delay device 23 to control the delay time. Consequently, an automatic adjustment of timing is done in one station as the line length of the circuit varies, so that the timing adjustment of each station can be omitted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11057877A JPS5444803A (en) | 1977-09-16 | 1977-09-16 | Synchronization system of loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11057877A JPS5444803A (en) | 1977-09-16 | 1977-09-16 | Synchronization system of loop circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5444803A true JPS5444803A (en) | 1979-04-09 |
Family
ID=14539382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11057877A Pending JPS5444803A (en) | 1977-09-16 | 1977-09-16 | Synchronization system of loop circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5444803A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6019339A (en) * | 1983-07-14 | 1985-01-31 | Toshiba Corp | Control method of data highway |
-
1977
- 1977-09-16 JP JP11057877A patent/JPS5444803A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6019339A (en) * | 1983-07-14 | 1985-01-31 | Toshiba Corp | Control method of data highway |
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