JPS5445532A - Interlock circuit - Google Patents
Interlock circuitInfo
- Publication number
- JPS5445532A JPS5445532A JP11280477A JP11280477A JPS5445532A JP S5445532 A JPS5445532 A JP S5445532A JP 11280477 A JP11280477 A JP 11280477A JP 11280477 A JP11280477 A JP 11280477A JP S5445532 A JPS5445532 A JP S5445532A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- synchronizing
- signal
- interlock circuit
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M11/00—Coding in connection with keyboards or like devices, i.e. coding of the position of operated keys
- H03M11/02—Details
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Electronic Switches (AREA)
- Input From Keyboards Or The Like (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To constitute the interlock circuit with priority, by using synchronous FF as the receiver of the switch input signal, using pulse different in frequency for the synchronizing signal of FF and giving priority between switch input signals. CONSTITUTION:The on-off condition of switches 2 to 4 by DC power supply 1 is converted into digital signal with circuits I to I'' and is given to synchronizing type FF II to II''. The synchronizing pulse obtained from the synchronizing signal set circuits III to III'' demultiplies the reference pulse (d) into two and further, demultiplies the pulse (e) having suitable phase delay into two, and constitutes the pulse having the frequency divided ratio and the phase lag as the pulse f having suitable phase delay. The gate circuits IV to IV'' setting the reset signal of FF are OR circuit inputting binary outputs (a), (b),...of FF and the output of the interlock circuit is given as Q output of FF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52112804A JPS5828966B2 (en) | 1977-09-19 | 1977-09-19 | interlock circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52112804A JPS5828966B2 (en) | 1977-09-19 | 1977-09-19 | interlock circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5445532A true JPS5445532A (en) | 1979-04-10 |
| JPS5828966B2 JPS5828966B2 (en) | 1983-06-20 |
Family
ID=14595935
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52112804A Expired JPS5828966B2 (en) | 1977-09-19 | 1977-09-19 | interlock circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5828966B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4886403A (en) * | 1972-02-17 | 1973-11-15 | ||
| JPS4976526U (en) * | 1972-10-18 | 1974-07-03 |
-
1977
- 1977-09-19 JP JP52112804A patent/JPS5828966B2/en not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4886403A (en) * | 1972-02-17 | 1973-11-15 | ||
| JPS4976526U (en) * | 1972-10-18 | 1974-07-03 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5828966B2 (en) | 1983-06-20 |
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