JPS5447444A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5447444A
JPS5447444A JP11272277A JP11272277A JPS5447444A JP S5447444 A JPS5447444 A JP S5447444A JP 11272277 A JP11272277 A JP 11272277A JP 11272277 A JP11272277 A JP 11272277A JP S5447444 A JPS5447444 A JP S5447444A
Authority
JP
Japan
Prior art keywords
bank
address
cycle
signal
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11272277A
Other languages
Japanese (ja)
Inventor
Osamu Kinoshita
Masahiko Kida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11272277A priority Critical patent/JPS5447444A/en
Publication of JPS5447444A publication Critical patent/JPS5447444A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To secure a constant access to the memory with no consciousness of the refresh cycle, by dividing the memory into two banks at the even and odd address sides and refreshing one bank while the other bank is being given an access. CONSTITUTION:The memory is divided into two: even bank 6 and odd bank 7 to possess the even and odd addresses. When the reading action is indicated for the even address, control circuit 1 selects access address signal 19 to address switch 4 and gives indication 17 to supply the access address signal to bank 6. at the same time, indication 16 is given to select refresh RF address signal 23 to address switch 5, and RF indication signal 11 is applied to bank 7 to start the RF cycle. After this, reading data output 21 given from bank 6 to output switch 8 via output switch signal 9. Thus, the reading cycle of bank 6 and the RF cycle of bank 7 are carried out simultaneously.
JP11272277A 1977-09-21 1977-09-21 Memory unit Pending JPS5447444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11272277A JPS5447444A (en) 1977-09-21 1977-09-21 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11272277A JPS5447444A (en) 1977-09-21 1977-09-21 Memory unit

Publications (1)

Publication Number Publication Date
JPS5447444A true JPS5447444A (en) 1979-04-14

Family

ID=14593881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11272277A Pending JPS5447444A (en) 1977-09-21 1977-09-21 Memory unit

Country Status (1)

Country Link
JP (1) JPS5447444A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061994A (en) * 1983-09-14 1985-04-09 Toshiba Corp Control circuit of dynamic memory
JPS61294694A (en) * 1985-06-20 1986-12-25 Mitsubishi Electric Corp Memory device
JPH04229486A (en) * 1990-12-27 1992-08-18 Nec Home Electron Ltd Memory access controller

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831030A (en) * 1971-08-26 1973-04-24
JPS4848044A (en) * 1971-10-20 1973-07-07
JPS5042754A (en) * 1973-08-20 1975-04-18
JPS50100933A (en) * 1974-01-04 1975-08-11
JPS5248441A (en) * 1975-05-28 1977-04-18 Hitachi Ltd Memory system
JPS5277640A (en) * 1975-12-24 1977-06-30 Nippon Telegr & Teleph Corp <Ntt> Refresh control system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4831030A (en) * 1971-08-26 1973-04-24
JPS4848044A (en) * 1971-10-20 1973-07-07
JPS5042754A (en) * 1973-08-20 1975-04-18
JPS50100933A (en) * 1974-01-04 1975-08-11
JPS5248441A (en) * 1975-05-28 1977-04-18 Hitachi Ltd Memory system
JPS5277640A (en) * 1975-12-24 1977-06-30 Nippon Telegr & Teleph Corp <Ntt> Refresh control system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6061994A (en) * 1983-09-14 1985-04-09 Toshiba Corp Control circuit of dynamic memory
JPS61294694A (en) * 1985-06-20 1986-12-25 Mitsubishi Electric Corp Memory device
JPH04229486A (en) * 1990-12-27 1992-08-18 Nec Home Electron Ltd Memory access controller

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