JPS5447520A - Initial state setting circuit - Google Patents

Initial state setting circuit

Info

Publication number
JPS5447520A
JPS5447520A JP11335277A JP11335277A JPS5447520A JP S5447520 A JPS5447520 A JP S5447520A JP 11335277 A JP11335277 A JP 11335277A JP 11335277 A JP11335277 A JP 11335277A JP S5447520 A JPS5447520 A JP S5447520A
Authority
JP
Japan
Prior art keywords
circuit
capacitor
delay time
ratch
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11335277A
Other languages
Japanese (ja)
Other versions
JPS6160455B2 (en
Inventor
Jiro Sakaguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11335277A priority Critical patent/JPS5447520A/en
Publication of JPS5447520A publication Critical patent/JPS5447520A/en
Publication of JPS6160455B2 publication Critical patent/JPS6160455B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Calculators And Similar Devices (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE: To increase the time constant prescribing the delay time for the automatic clear circuit of the electronic desk computer and the like by utilizing the charge share between plural numbers of capacitors, and thus to obtain the reset signal of a long delay time through addition of a small number of the elements.
CONSTITUTION: After MOSFETQ5WQ10 constituting the ratch circuit is turned on, delay time deciding capacitor C1 is charged gradually via MOSFETQ1, Q2 and Q3 of the switching element which is turned on and off according to clock pulse CP. The ratch circuit is triggered by the charging voltage, the state of the ratch circuit is inverted with delay of a fixed time after generation of pulse CP, and thus the initial state signal is produced through ratch circuit. Capacitor C2 featuring a smaller capacity than delay time deciding capacitor C1 is connected to the ratch circuit at the joint between switching element Q2 and Q3. Then the potential of the opposite- phase potential to the charge of capacitor C1 is charged in accordance with pulse
COPYRIGHT: (C)1979,JPO&Japio
JP11335277A 1977-09-22 1977-09-22 Initial state setting circuit Granted JPS5447520A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11335277A JPS5447520A (en) 1977-09-22 1977-09-22 Initial state setting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11335277A JPS5447520A (en) 1977-09-22 1977-09-22 Initial state setting circuit

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP4912684A Division JPS605973B2 (en) 1984-03-16 1984-03-16 switching circuit

Publications (2)

Publication Number Publication Date
JPS5447520A true JPS5447520A (en) 1979-04-14
JPS6160455B2 JPS6160455B2 (en) 1986-12-20

Family

ID=14610080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11335277A Granted JPS5447520A (en) 1977-09-22 1977-09-22 Initial state setting circuit

Country Status (1)

Country Link
JP (1) JPS5447520A (en)

Also Published As

Publication number Publication date
JPS6160455B2 (en) 1986-12-20

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