JPS5449037A - Timing contol system of memory unit - Google Patents

Timing contol system of memory unit

Info

Publication number
JPS5449037A
JPS5449037A JP11514577A JP11514577A JPS5449037A JP S5449037 A JPS5449037 A JP S5449037A JP 11514577 A JP11514577 A JP 11514577A JP 11514577 A JP11514577 A JP 11514577A JP S5449037 A JPS5449037 A JP S5449037A
Authority
JP
Japan
Prior art keywords
register
time
gate
memory unit
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11514577A
Other languages
Japanese (ja)
Other versions
JPS5856196B2 (en
Inventor
Akio Kimura
Tadashi Kawanobe
Yoshio Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NEC Corp
NTT Inc
Original Assignee
Fujitsu Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP52115145A priority Critical patent/JPS5856196B2/en
Publication of JPS5449037A publication Critical patent/JPS5449037A/en
Publication of JPS5856196B2 publication Critical patent/JPS5856196B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Abstract

PURPOSE:To eliminate the delay of access operation by leading out a terminal from the timing chain circuit of a memory unit and by connecting a gate circuit to it. CONSTITUTION:Signals are applied to starting signal register 10, write register 20, refresh register 21, normal address register 30, and write data register 40 as shown in the figure and, for example, at the time of a read/write cycle, memory address signal MAD with a certain delay from a normal address rise is applied from address switching circuit 2 to meory array 1. Then, timing chain circuit 4 outputs signals Tcl and Tc2, which are delayed from output EN of register 10 by Td1 and Td2, to AND gate 5 and OR gate 6. Consequently, a tip enable signal at the time of reading and writing/refreshing is generated independently, and the access time at the time of reading can be shortened.
JP52115145A 1977-09-27 1977-09-27 Storage device timing control method Expired JPS5856196B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52115145A JPS5856196B2 (en) 1977-09-27 1977-09-27 Storage device timing control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52115145A JPS5856196B2 (en) 1977-09-27 1977-09-27 Storage device timing control method

Publications (2)

Publication Number Publication Date
JPS5449037A true JPS5449037A (en) 1979-04-18
JPS5856196B2 JPS5856196B2 (en) 1983-12-13

Family

ID=14655410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52115145A Expired JPS5856196B2 (en) 1977-09-27 1977-09-27 Storage device timing control method

Country Status (1)

Country Link
JP (1) JPS5856196B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157895A (en) * 1983-02-28 1984-09-07 Nec Corp Integrated circuit device incorporating read-only memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157895A (en) * 1983-02-28 1984-09-07 Nec Corp Integrated circuit device incorporating read-only memory

Also Published As

Publication number Publication date
JPS5856196B2 (en) 1983-12-13

Similar Documents

Publication Publication Date Title
KR100254071B1 (en) Synchronous dram
KR950034253A (en) Synchronous Memory with Parallel Output Data Path
JPS54152931A (en) Semiconductor memory device
ATE24617T1 (en) DIRECT ACCESS STORAGE ARRANGEMENTS.
GB1477236A (en) Computer memory read delay
JPS6446162A (en) Vector processor
KR960042730A (en) Semiconductor storage device
KR910015999A (en) Semiconductor memory device
KR960025011A (en) Data input / output detection circuit of memory device
JPS5449037A (en) Timing contol system of memory unit
TW349226B (en) A test method of high speed memory devices in which limit conditions for the clock signals are defined
KR950020127A (en) Semiconductor memory circuit control method
JPS55134442A (en) Data transfer unit
JPS5447438A (en) Control system for scratch memory
KR950006856A (en) Column Decoder Enable Signal Generation Circuit of Semiconductor Device
JPS57195374A (en) Sequential access storage device
JPS53107240A (en) Control system of register memory
JPS54145444A (en) Control system of buffer memory
JPS56168267A (en) Logical device
JPS6461835A (en) Sequential access memory
JPS54123841A (en) Semiconductor integrated memory element
JPS57147183A (en) Shift register
JPS6425257A (en) Memory controller
JPS6482389A (en) Semiconductor memory
JPS5720979A (en) Memory control system