JPS5452930A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5452930A
JPS5452930A JP11960877A JP11960877A JPS5452930A JP S5452930 A JPS5452930 A JP S5452930A JP 11960877 A JP11960877 A JP 11960877A JP 11960877 A JP11960877 A JP 11960877A JP S5452930 A JPS5452930 A JP S5452930A
Authority
JP
Japan
Prior art keywords
block
contents
memory
registers
data transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11960877A
Other languages
Japanese (ja)
Inventor
Masao Uchiumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11960877A priority Critical patent/JPS5452930A/en
Publication of JPS5452930A publication Critical patent/JPS5452930A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To decrease the power consumption for the memory unit using the serial memory element under use, by providing the address register with evey memory block and switching the clock period by the block under data transmission and the block under data holding. CONSTITUTION:Address registers 4-6 are provided with every 1-3 memory blocks in the memory unit using the serial memory element. Furthermore, address comparator circuit 8 is added to compare the contents of address registers 7 under transmission of the present data with the contents of registers 4-6, along with clock circuit 9 which performs switching between the high frequency clock for data transmission and the low frequency clock for data memory holding purpose. Thus, the contents of registers 4-6 are compared with the contents of register 7, and the block accompanied by no data transmission is used as the low frequency clock. While the block causing the data transmission is used as the high frequency block. Thus, the power comsumption can be decreased.
JP11960877A 1977-10-05 1977-10-05 Memory unit Pending JPS5452930A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11960877A JPS5452930A (en) 1977-10-05 1977-10-05 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11960877A JPS5452930A (en) 1977-10-05 1977-10-05 Memory unit

Publications (1)

Publication Number Publication Date
JPS5452930A true JPS5452930A (en) 1979-04-25

Family

ID=14765610

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11960877A Pending JPS5452930A (en) 1977-10-05 1977-10-05 Memory unit

Country Status (1)

Country Link
JP (1) JPS5452930A (en)

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