JPS5453837A - Memory error report system - Google Patents

Memory error report system

Info

Publication number
JPS5453837A
JPS5453837A JP12029277A JP12029277A JPS5453837A JP S5453837 A JPS5453837 A JP S5453837A JP 12029277 A JP12029277 A JP 12029277A JP 12029277 A JP12029277 A JP 12029277A JP S5453837 A JPS5453837 A JP S5453837A
Authority
JP
Japan
Prior art keywords
error
memory
circuit
cpu
memory error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12029277A
Other languages
Japanese (ja)
Inventor
Yukio Soma
Takamitsu Tsuchimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12029277A priority Critical patent/JPS5453837A/en
Publication of JPS5453837A publication Critical patent/JPS5453837A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To prevent the overhead of software from increasing, by inhibiting an error, which can be corrected, from being reported to CPU if the error like this has ever occurred on the memory where the error above has occurred.
CONSTITUTION: Memory 1 is divided into a number of memory units and is provided with memory error storage parts, which correspond to memory units respectively, as weel as ont-bit error detector circuit 2. If a one-bit error is detected when chip selection line CS2 is selected, AND circuit 3-2 outputs "1". Then, when FF4-2 is set, AND circuit 5-2 outputs "1" and this output "1" is outputted to CPU through OR circuit 6. Even if selector CS2 is selected and another one-bit error is detected afterward, the error is not reported to CPU. Thus, the needless report of memory error is not performed, thereby preventing the overhead of software from increasing
COPYRIGHT: (C)1979,JPO&Japio
JP12029277A 1977-10-06 1977-10-06 Memory error report system Pending JPS5453837A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12029277A JPS5453837A (en) 1977-10-06 1977-10-06 Memory error report system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12029277A JPS5453837A (en) 1977-10-06 1977-10-06 Memory error report system

Publications (1)

Publication Number Publication Date
JPS5453837A true JPS5453837A (en) 1979-04-27

Family

ID=14782620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12029277A Pending JPS5453837A (en) 1977-10-06 1977-10-06 Memory error report system

Country Status (1)

Country Link
JP (1) JPS5453837A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848297A (en) * 1981-09-14 1983-03-22 Nec Corp Processing system for 1-bit error fault of storage device
JPS5862900A (en) * 1981-10-08 1983-04-14 Nec Corp Processing system for single bit error of memory
EP1481805A2 (en) 1996-07-31 2004-12-01 Canon Kabushiki Kaisha A substrate for an ink jet recording head

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848297A (en) * 1981-09-14 1983-03-22 Nec Corp Processing system for 1-bit error fault of storage device
JPS5862900A (en) * 1981-10-08 1983-04-14 Nec Corp Processing system for single bit error of memory
EP1481805A2 (en) 1996-07-31 2004-12-01 Canon Kabushiki Kaisha A substrate for an ink jet recording head

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