JPS5453845A - Data processing unit using microprogram control system - Google Patents

Data processing unit using microprogram control system

Info

Publication number
JPS5453845A
JPS5453845A JP12076377A JP12076377A JPS5453845A JP S5453845 A JPS5453845 A JP S5453845A JP 12076377 A JP12076377 A JP 12076377A JP 12076377 A JP12076377 A JP 12076377A JP S5453845 A JPS5453845 A JP S5453845A
Authority
JP
Japan
Prior art keywords
registers
detailing
error
register
microprogram control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12076377A
Other languages
Japanese (ja)
Inventor
Hisayoshi Tsubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12076377A priority Critical patent/JPS5453845A/en
Publication of JPS5453845A publication Critical patent/JPS5453845A/en
Pending legal-status Critical Current

Links

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make it possible to obtain directly up-to-data error information from error detailing registers by providing an error register for microprogram control information independently so that this register can be set together with detailing registers at the same time.
CONSTITUTION: Register 5 stores that error detector circuits 4 and 3 have detected and error. Meanwhile, detailing registers 6 and 7 are provided correspondingly to circuits 3 and 4 which are set by the same timing clock as register 5. Then, NAND circuit 14, 15, 18 and 19 inhibit detailing registers 6 and 7 from being reset by a microprogram, and simultaneously, reset detailing registers other than the detailing register corresponding to one error detector circuit, at least. Then, the state where one of registers 6 and 7, at least, is set and contents of registers 6 and 7 are displayed on displays 8 and 9. Thus, up-to-date error information can be obtained directly from registers 6 and 7 at an arbitray time
COPYRIGHT: (C)1979,JPO&Japio
JP12076377A 1977-10-06 1977-10-06 Data processing unit using microprogram control system Pending JPS5453845A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12076377A JPS5453845A (en) 1977-10-06 1977-10-06 Data processing unit using microprogram control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12076377A JPS5453845A (en) 1977-10-06 1977-10-06 Data processing unit using microprogram control system

Publications (1)

Publication Number Publication Date
JPS5453845A true JPS5453845A (en) 1979-04-27

Family

ID=14794381

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12076377A Pending JPS5453845A (en) 1977-10-06 1977-10-06 Data processing unit using microprogram control system

Country Status (1)

Country Link
JP (1) JPS5453845A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123534A (en) * 1985-11-22 1987-06-04 Nec Corp Input and output control system for electronic journal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62123534A (en) * 1985-11-22 1987-06-04 Nec Corp Input and output control system for electronic journal

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