JPS5455157A - Processor for analog signal - Google Patents

Processor for analog signal

Info

Publication number
JPS5455157A
JPS5455157A JP12206377A JP12206377A JPS5455157A JP S5455157 A JPS5455157 A JP S5455157A JP 12206377 A JP12206377 A JP 12206377A JP 12206377 A JP12206377 A JP 12206377A JP S5455157 A JPS5455157 A JP S5455157A
Authority
JP
Japan
Prior art keywords
signal
address
signals
synchronizer
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12206377A
Other languages
Japanese (ja)
Inventor
Tetsuo Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12206377A priority Critical patent/JPS5455157A/en
Publication of JPS5455157A publication Critical patent/JPS5455157A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To shorten a signal read-out time to a CPU, etc., by providing an address change-over circuit which changes over address signals from a synchronizer.
CONSTITUTION: Analog signals from analog signal supply 1 are indicated by the address signal of synchronizer 7 and then supplied to A-d converter 4 via analog switch 2 which is switched sequentially every constant time. Through the instruction of synchronizer 7, A-D converter 4 converts analog signals into digital signals, which are stored in a place, indicated by the address signal of synchronizer 7, in digital memory 6. In order to read signals in CPU5 for the purpose of a signal process, a signal assigning the fixed address of memory 6 is transmitted from CPU5. This address signal arrives at memory 6 and the signal of analog signal source 1 is read out as a digital signal being delayed by the only operation time of memory 6, and processed
COPYRIGHT: (C)1979,JPO&Japio
JP12206377A 1977-10-11 1977-10-11 Processor for analog signal Pending JPS5455157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12206377A JPS5455157A (en) 1977-10-11 1977-10-11 Processor for analog signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12206377A JPS5455157A (en) 1977-10-11 1977-10-11 Processor for analog signal

Publications (1)

Publication Number Publication Date
JPS5455157A true JPS5455157A (en) 1979-05-02

Family

ID=14826698

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12206377A Pending JPS5455157A (en) 1977-10-11 1977-10-11 Processor for analog signal

Country Status (1)

Country Link
JP (1) JPS5455157A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04185116A (en) * 1990-11-20 1992-07-02 Japan Radio Co Ltd D/a converter circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04185116A (en) * 1990-11-20 1992-07-02 Japan Radio Co Ltd D/a converter circuit

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