JPS5457919A - Generation system for memory circuit protective alarm - Google Patents

Generation system for memory circuit protective alarm

Info

Publication number
JPS5457919A
JPS5457919A JP12487977A JP12487977A JPS5457919A JP S5457919 A JPS5457919 A JP S5457919A JP 12487977 A JP12487977 A JP 12487977A JP 12487977 A JP12487977 A JP 12487977A JP S5457919 A JPS5457919 A JP S5457919A
Authority
JP
Japan
Prior art keywords
processing part
disconnected
data
power source
output end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12487977A
Other languages
Japanese (ja)
Other versions
JPS6110860B2 (en
Inventor
Tomohiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP12487977A priority Critical patent/JPS5457919A/en
Publication of JPS5457919A publication Critical patent/JPS5457919A/en
Publication of JPS6110860B2 publication Critical patent/JPS6110860B2/ja
Granted legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To prevent the erroneous operation of users to utilize effectively the operation system by detecting that an external memory has been disconnected from the arithmetic processing part and issuing alarm in a minicomputer.
CONSTITUTION: This system is provided with arithmetic processing part 1 which executes a series of incorporated micro instructions, voltage level detection part 14 of power source 3 for the processing part, external memory 5 which is driven by power source 3 or private power source 7 to perform the data exchange to processing part 1 and has the data input/output end connected or disconnected according to signals from detection part 14, and decision code data setting parts 12 and 13 which set data identically when the data input/output end of the memory is disconnected. Then, processing part 1 decides data set in setting parts 12 and 13 in a specific step of instructions and detects that the data input/output end of memory 5 has been disconnected and generates alarm on display part 11
COPYRIGHT: (C)1979,JPO&Japio
JP12487977A 1977-10-18 1977-10-18 Generation system for memory circuit protective alarm Granted JPS5457919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12487977A JPS5457919A (en) 1977-10-18 1977-10-18 Generation system for memory circuit protective alarm

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12487977A JPS5457919A (en) 1977-10-18 1977-10-18 Generation system for memory circuit protective alarm

Publications (2)

Publication Number Publication Date
JPS5457919A true JPS5457919A (en) 1979-05-10
JPS6110860B2 JPS6110860B2 (en) 1986-03-31

Family

ID=14896343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12487977A Granted JPS5457919A (en) 1977-10-18 1977-10-18 Generation system for memory circuit protective alarm

Country Status (1)

Country Link
JP (1) JPS5457919A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3011990U (en) * 1994-12-02 1995-06-06 株式会社ワイズ Seal

Also Published As

Publication number Publication date
JPS6110860B2 (en) 1986-03-31

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