JPS5458184A - Sequence control circuit - Google Patents

Sequence control circuit

Info

Publication number
JPS5458184A
JPS5458184A JP12451577A JP12451577A JPS5458184A JP S5458184 A JPS5458184 A JP S5458184A JP 12451577 A JP12451577 A JP 12451577A JP 12451577 A JP12451577 A JP 12451577A JP S5458184 A JPS5458184 A JP S5458184A
Authority
JP
Japan
Prior art keywords
clock
terminal
added
sequence control
timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12451577A
Other languages
Japanese (ja)
Inventor
Noboru Yamaguchi
Yuzo Kida
Masaru Shibukawa
Kazuo Minorikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12451577A priority Critical patent/JPS5458184A/en
Publication of JPS5458184A publication Critical patent/JPS5458184A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the sequence cntrol circuit to be constituted without a logic change even when the object is changed by means of capabling of changing over a clock added to the timer of a sequence control circuit into whether a fixed frequency or a frequency proportional to an inherent constant of the control object.
CONSTITUTION: 1 is a timer for the purpose of progressing sequence control, and 2 is a multipex circuit, and a clock of a fixed frequency is added on a terminal 3, and a clock of a frequency proportional to an inherent constant of the control object, is added. A terminal 5 is the one to select whichever clock may be used, and when this terminal is zero, a clock from the teminal 3 is added, and when this terminal is 1, a clock from the terminal 4. is added to the timer 1
COPYRIGHT: (C)1979,JPO&Japio
JP12451577A 1977-10-19 1977-10-19 Sequence control circuit Pending JPS5458184A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12451577A JPS5458184A (en) 1977-10-19 1977-10-19 Sequence control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12451577A JPS5458184A (en) 1977-10-19 1977-10-19 Sequence control circuit

Publications (1)

Publication Number Publication Date
JPS5458184A true JPS5458184A (en) 1979-05-10

Family

ID=14887382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12451577A Pending JPS5458184A (en) 1977-10-19 1977-10-19 Sequence control circuit

Country Status (1)

Country Link
JP (1) JPS5458184A (en)

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