JPS5459015A - Propagation delay time compensating receiver - Google Patents

Propagation delay time compensating receiver

Info

Publication number
JPS5459015A
JPS5459015A JP12631677A JP12631677A JPS5459015A JP S5459015 A JPS5459015 A JP S5459015A JP 12631677 A JP12631677 A JP 12631677A JP 12631677 A JP12631677 A JP 12631677A JP S5459015 A JPS5459015 A JP S5459015A
Authority
JP
Japan
Prior art keywords
circuit
delay time
tau0
tau1
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12631677A
Other languages
Japanese (ja)
Inventor
Motoyasu Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12631677A priority Critical patent/JPS5459015A/en
Publication of JPS5459015A publication Critical patent/JPS5459015A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00Modulated-carrier systems
    • H04L27/18Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22Demodulator circuits; Receiver circuits
    • H04L27/227Demodulator circuits; Receiver circuits using coherent demodulation
    • H04L27/2275Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
    • H04L27/2276Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals using frequency multiplication or harmonic tracking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Filters And Equalizers (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To reduce the transient answer phase errors of various phase synchronous loops as well as the phase fluctuation of the demodulated data signals, by suppressing the differential propagation delay time at the stage before demodulation. CONSTITUTION:Input PSK modulation wave 20 is branched off (1) into the main signal and the control signal in a proper ratio, and the main signal rceives the delay time of tau1 via delay circuit 2 to be then applied to delay circuit 3. While the control signal receives the delay time of tau0 through delay circuit 4 to be then applied to multiplying circuit 5. The center delay time tau0 of circuit 3 and delay time tau1 of circuit 5-11 are offset by delay time tau0 of circuit 4 and delay time tau1 of circuit 2 respectively, thus standardizing tau0+tau1 to zero. At the same time, tuning circuit 6 extracts the carrier component from the output of circuit 5 and then differentiates the component discriminating circuit 8 via amplitude limit circuit 7. And the slow frequency fluctuation which is contained in the output of circuit 8 via the PSK modulator, the transmission/reception local oscillation and others is eliminated through capacitor 9 with then integration 10. Then the output of the integration undergoes gain adjustment 11 properly to control circuit 3. Thus, the differential propagation delay time can be suppressed for the main signal.
JP12631677A 1977-10-19 1977-10-19 Propagation delay time compensating receiver Pending JPS5459015A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12631677A JPS5459015A (en) 1977-10-19 1977-10-19 Propagation delay time compensating receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12631677A JPS5459015A (en) 1977-10-19 1977-10-19 Propagation delay time compensating receiver

Publications (1)

Publication Number Publication Date
JPS5459015A true JPS5459015A (en) 1979-05-12

Family

ID=14932161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12631677A Pending JPS5459015A (en) 1977-10-19 1977-10-19 Propagation delay time compensating receiver

Country Status (1)

Country Link
JP (1) JPS5459015A (en)

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